Systems and methods for reducing register bank conflicts based on software hint and hardware thread switch

Abstract

Mechanisms for reducing register bank conflicts based on software hint and hardware thread switch are disclosed. In some embodiments, an apparatus for thread switching includes a graphics processing unit (GPU) that includes a plurality of register banks to store operands that are assigned at least partially to avoid register bank conflicts. A decoding circuitry checks a thread switching field of a first instruction to be executed by a first thread. The GPU performs a thread switch mechanism to cause a second instruction to be executed by a second thread when the thread switching field of the first instruction is set.

1 . An apparatus to perform thread switching, comprising:
 a graphics processing unit (GPU), including:
 a plurality of register banks to store operands that are assigned at least partially to avoid register bank conflicts; and 
 decoding circuitry to check a thread switching field of a first instruction to execute with a first thread with the thread switching field to indicate whether a register bank conflict exists based on whether a first operand of the first instruction and a second operand of a second instruction of the first thread both being assigned in the same register bank. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the thread switching field comprises a thread switching bit of the first instruction. 
     
     
         3 . The apparatus of  claim 2 , further comprising:
 a thread scheduler to perform a first thread switch to cause a second instruction to execute with a second thread when the thread switching bit of the first instruction is set.   
     
     
         4 . The apparatus of  claim 3 , wherein the first thread switch to cause a second instruction to execute with a second thread due to a register bank conflict between a first operand of the first instruction and a second operand of a different instruction. 
     
     
         5 . The apparatus of  claim 4 , wherein the first and second operands are assigned to the same register bank and read port of the register bank. 
     
     
         6 . The apparatus of  claim 2 , wherein the thread scheduler to perform a second thread switch when the thread switching bit of the first instruction is not set. 
     
     
         7 . A graphics processing unit (GPU), comprising:
 a register file array having a plurality of register banks to store operands that are assigned at least partially to avoid register bank conflicts; and   circuitry to check a thread switching field of a first instruction to execute with a first thread with the thread switching field to indicate whether a register bank conflict exists based on whether a first operand of the first instruction and a second operand of a second instruction of the first thread both being assigned in the same register bank.   
     
     
         8 . The graphics processing unit of  claim 7 , wherein the thread switching field comprises a thread switching bit of the first instruction. 
     
     
         9 . The graphics processing unit of  claim 8 , further comprising:
 a thread scheduler to perform a first thread switch to cause a second instruction to execute with a second thread when the thread switching bit of the first instruction is set.   
     
     
         10 . The graphics processing unit of  claim 9 , wherein the first thread switch to cause a second instruction to execute with a second thread due to a register bank conflict between a first operand of the first instruction and a second operand of a different instruction. 
     
     
         11 . The graphics processing unit of  claim 10 , wherein the first thread switch to cause no additional clock cycles to reduce register bank conflicts. 
     
     
         12 . The graphics processing unit of  claim 8 , wherein the thread scheduler to perform a second thread switch when the thread switching bit of the first instruction is not set. 
     
     
         13 . A method for thread switching, comprising:
 assigning source operands of instructions to different register banks or ports to at least partially avoid a register bank conflict;   performing instruction scheduling including determining an order of the instructions; and   generating a thread switching field on a first instruction among the ordered instructions with the thread switching field to indicate whether a register bank conflict exists based on whether a first operand of the first instruction and a second operand of a second instruction of the first thread both being assigned in the same register bank.   
     
     
         14 . The method of  claim 13 , wherein generating the thread switching field comprises setting a thread switching bit with the first instruction based on detection of register bank conflicts. 
     
     
         15 . The method of  claim 13 , further comprising:
 determining whether any bank conflicts exist between sequentially ordered instructions including the first instruction and a second different instruction.   
     
     
         16 . The method of  claim 13 , further comprising:
 generating binary encoding of the instructions.   
     
     
         17 . The method of  claim 13 , further comprising:
 determining whether any bank conflicts exist after the instruction scheduling; and   modifying instruction scheduling to reduce bank conflicts if bank conflicts exist.   
     
     
         18 . The method of  claim 14 , further comprising:
 checking, with a decoding circuitry, the thread switching bit of the first instruction; and   performing a forced thread switch from a first thread to a second thread if the thread switching bit is set.   
     
     
         19 . A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
 assigning source operands of instructions to different register banks or ports to at least partially avoid a register bank conflict;   performing instruction scheduling including determining an order of the instructions; and   generating a thread switching field on a first instruction among the ordered instructions with the thread switching field to indicate whether a register bank conflict exists based on whether a first operand of the first instruction and a second operand of a second instruction of the first thread both being assigned in the same register bank.   
     
     
         20 . The medium of  claim 19 , wherein generating the thread switching field comprises setting a thread switching bit with the first instruction based on detection of register bank conflicts. 
     
     
         21 . The medium of  claim 19 , further comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
 determining whether any bank conflicts exist between sequentially ordered instructions including the first instruction and a second different instruction.