Reconfigurable reduced instruction set computer processor architecture with fractured cores

Abstract

Systems and methods for reconfiguring a reduced instruction set computer processor architecture are disclosed. Exemplary implementations may: provide a primary processing core consisting of a RISC processor; provide a node wrapper associated with each of the plurality of secondary cores, the node wrapper comprising access memory associates with each secondary core, and a load/unload matrix associated with each secondary core; operate the architecture in a manner in which, for at least one core, data is read from and written to the at least cache memory in a control-centric mode; the secondary cores are selectively partitioned to operate in a streaming mode wherein data streams out of the corresponding secondary core into the main memory and other ones of the plurality of secondary cores.

What is claimed is: 
     
         1 . A reduced instruction set computer processor architecture comprising:
 multiple RISC processors each defining a primary processing core in a control-centric mode, each primary processing core comprising:
 a main memory; 
 at least one cache memory; 
 at least one arithmetic logic unit capable of reading from and writing to the at least one cache memory in a control-centric mode; 
   a node wrapper associated with each of the primary cores, the node wrapper being operable to define a plurality of secondary cores by configuring network connections in a manner that defines at least one pipeline to allow data to stream out of arithmetic logic units into the main memory and other ones of the plurality of arithmetic logic units in a streaming mode, the node wrapper comprising;
 access memory associate with each arithmetic logic unit; 
 at least one load/unload matrix associated with each arithmetic logic unit; and 
 a partitioning logic module configured to individually configure each of the primary cores to operate in the streaming mode or the control-centric mode. 
   
     
     
         2 . A method for reconfiguring a reduced instruction set computer processor architecture, the method comprising:
 providing a plurality of primary processing cores defined by RISC processors, each primary processing core comprising a main memory, at least one cache memory, and a plurality of arithmetic logic units;   providing a node wrapper associated with each primary core, the node wrapper comprising access memory associated with each arithmetic logic unit, and a load/unload matrix associated with each arithmetic logic unit;   operating the architecture in a manner in which, for at least primary core, data is read from and written to the at least cache memory in a control-centric mode; and   selectively configuring at least one primary core to operate in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.