Power gate with metal on both sides

Abstract

An apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side defined by a gate electrode and an opposite second side; and a gated supply grid disposed on the second side of the structure, wherein a drain of the at least one of the plurality of transistor devices is coupled to the gated supply grid. A method including providing a supply from a package substrate to power gate transistors in a device layer of a circuit structure, the transistors coupled to circuitry operable to receive a gated supply from the power gate transistors; and distributing the gated supply from the power gate transistors to the circuitry using a grid on an underside of the device layer.

1 . A method comprising:
 providing a supply from a package substrate to power gate transistors in a device layer of a circuit structure, the transistors coupled to circuitry operable to receive a gated supply from the power gate transistors; and   distributing the gated supply from the power gate transistors to the circuitry using a grid on an underside of the device layer.   
     
     
         2 . The method of  claim 1 , wherein providing a supply to power gate transistors comprises coupling to the transistors from the underside of the device layer. 
     
     
         3 . The method of  claim 1 , wherein providing a supply to power gate transistors comprises distributing the supply from the package substrate using a grid on the underside of the device layer. 
     
     
         4 . The method of  claim 1 , wherein distributing the gated supply from the power gate transistors comprises coupling the transistors to the grid from the underside of the transistors. 
     
     
         5 . The method of  claim 1 , further comprising controlling the gated supply from a control line coupled to the transistors on a side opposite the underside of the transistors. 
     
     
         6 . The method of  claim 1 , further comprising distributing a ground grid on the underside of the device layer, the ground grid coupled to the circuitry. 
     
     
         7 . A method of fabricating an apparatus, the method comprising:
 forming a circuit structure comprising a device stratum comprising a plurality of transistor devices, the device stratum having a first side and a second side opposite the first side, each of the plurality of transistors comprising a gate electrode on the first side of the device stratum; and   forming a gated supply grid on the second side of the device stratum, wherein a drain of the at least one of the plurality of transistor devices is coupled to the gated supply grid, wherein the drain of the at least one of the plurality of transistor devices is coupled to the gated supply grid through a contact, the contact on the second side of the device stratum and extending between the gated supply grid and the second side of the device stratum but not into the device stratum.   
     
     
         8 . The method of  claim 7 , further comprising forming a supply grid on the second side of the device stratum, wherein a source of at least one of the plurality of transistor devices is coupled to the supply grid. 
     
     
         9 . The method of  claim 7 , further comprising forming a control line on a first side of the device stratum, wherein the gate electrode of the at least one of the plurality of transistor devices is coupled to the control line. 
     
     
         10 . The method of  claim 10 , wherein the gate electrode of the at least one of the plurality of transistor devices is coupled to the control line through a gate contact projecting between the device and the control line and the drain of the device is coupled to the gated supply grid through a junction contact projecting between the device and the gated supply grid. 
     
     
         11 . The method of  claim 8 , further comprising forming a contact point operable to couple the circuit structure to an external power source, the contact point coupled to the supply grid on the second side of the device stratum. 
     
     
         12 . The method of  claim 7 , wherein the gated supply grid comprises a power grid, the method further comprising forming a ground grid on the second side of the device stratum. 
     
     
         13 . The method of  claim 7 , wherein the at least one of the transistor devices comprises a non-planar transistor device comprising a fin and the gate electrode is disposed on the channel region of the fin. 
     
     
         14 . A method of fabricating a system, the method comprising:
 providing comprising a package substrate comprising a supply connection; and   coupling a die to the package substrate, the die comprising:   (i) core logic circuitry to receive one or more gated supplies, and   (ii) a plurality of transistors defining a device layer and coupled between the supply connection and the core logic circuitry to controllably provide the one or more gated supplies to the core logic circuitry, the device layer having a first side and an underside opposite the first side, each of the plurality of transistors comprising a gate electrode on the first side of the device layer, wherein the gated supplies to the circuitry is routed on the underside of the device layer, wherein a drain of at least one of the plurality of transistors is coupled to the gated supplies through a contact, the contact on the underside of the device stratum and extending between the gated supplies and the underside of the device layer but not into the device layer.   
     
     
         15 . The method of  claim 14 , wherein the one or more gated supplies are coupled to the plurality of transistors from the underside of the device layer. 
     
     
         16 . The method of  claim 14 , wherein a supply connection to the power gate transistors comprises a grid on the underside of the device layer. 
     
     
         17 . The method of  claim 16 , wherein distributing the gated supply from the power gate transistors comprises coupling the transistors to the grid from the underside of the device layer. 
     
     
         18 . The method of  claim 14 , further comprising controlling the gated supply from a control line coupled to the plurality of transistors on the first side of the device layer. 
     
     
         19 . The method of  claim 14 , wherein at least one of the plurality of transistors comprises a non-planar transistor.