System and method for handling floating point hardware exception

Abstract

A method includes receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data to generate an output result. The method also includes determining whether the output result is going to cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data. The method further includes converting a value of the output result to a modified value responsive to the determining that the output result is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data.

What is claimed is: 
     
         1 . A computer-implemented method comprising:
 receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data to generate an output result;   determining whether the output result is going to cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data; and   converting a value of the output result to a modified value responsive to the determining that the output result is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data.   
     
     
         2 . The method of  claim 1 , wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, an add-reduce, or negation operation. 
     
     
         3 . The method of  claim 1 , wherein the floating point arithmetic operation is selected from one of maximum, minimum, max-reduce, or min-reduce. 
     
     
         4 . The method of  claim 1 , wherein the floating point arithmetic operation is selected from one of multiplication or divisional operation. 
     
     
         5 . The method of  claim 1 , wherein the floating point arithmetic operation is converting from a first floating point to a second floating point if the input data is less than a threshold and from a third floating point to a fourth floating point if the input is greater than the threshold. 
     
     
         6 . The method of  claim 1 , wherein the floating arithmetic operation is converting the input data from a floating point to an integer value. 
     
     
         7 . The method of  claim 1 , wherein the converting comprises setting a value of the output result to zero if a value of the output result is a denormal number. 
     
     
         8 . The method of  claim 1 , wherein the converting comprises setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity. 
     
     
         9 . The method of  claim 1 , wherein the converting comprises setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity. 
     
     
         10 . The method of  claim 1  further comprising raising an out-of-bound flag if the output result is a positive infinity, a negative infinity, or a denormal number. 
     
     
         11 . The method of  claim 1  further comprising raising a divide-by-zero flag when the floating point arithmetic operation is a division and wherein a dividend is a nonzero number and divisor is a zero number. 
     
     
         12 . A computer-implemented method comprising:
 receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data to generate an output result;   determining whether the output result is going to cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data; and   eliminating the floating point hardware exception responsive to determining that the output result is going to cause the floating point hardware exception by performing one or more of:
 setting a value of the output result to zero if a value of the output result is a denormal number; 
 setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity; and 
 setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity. 
   
     
     
         13 . The method of  claim 12 , wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, an add-reduce, or negation operation. 
     
     
         14 . The method of  claim 12 , wherein the floating point arithmetic operation is selected from one of maximum, minimum, max-reduce, or min-reduce. 
     
     
         15 . The method of  claim 12 , wherein the floating point arithmetic operation is selected from one of multiplication or divisional operation. 
     
     
         16 . The method of  claim 12 , wherein the floating point arithmetic operation is converting from a first floating point to a second floating point if the input data is less than a threshold and from a third floating point to a fourth floating point if the input is greater than the threshold. 
     
     
         17 . The method of  claim 12 , wherein the floating arithmetic operation is converting the input data from a floating point to an integer value. 
     
     
         18 . The method of  claim 12  further comprising raising an out-of-bound flag if the output result is a positive infinity, a negative infinity, or a denormal number. 
     
     
         19 . The method of  claim 12  further comprising raising a divide-by-zero flag when the floating point arithmetic operation is a division and wherein a dividend is a nonzero number and divisor is a zero number. 
     
     
         20 . A system comprising:
 a logic engine configured to receive an input data for arithmetic operation to be operated on by a floating point arithmetic operating unit to generate an output result, wherein the logic engine is configured to determine whether the output result is going to cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data; and   a convertor engine configured to convert a value of the output result to a modified value responsive to the determining that the output result generates the floating point hardware exception, wherein the modified value eliminates generation of the floating point hardware exception responsive to the floating point arithmetic operation on the input data.   
     
     
         21 . The system of  claim 20 , wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, an add-reduce, or negation operation. 
     
     
         22 . The system of  claim 20 , wherein the floating point arithmetic operation is selected from one of maximum, minimum, max-reduce, or min-reduce. 
     
     
         23 . The system of  claim 20 , wherein the floating point arithmetic operation is selected from one of multiplication or divisional operation. 
     
     
         24 . The system of  claim 20 , wherein the floating point arithmetic operation is converting from a first floating point to a second floating point if the input data is less than a threshold and from a third floating point to a fourth floating point if the input is greater than the threshold. 
     
     
         25 . The system of  claim 20 , wherein the floating arithmetic operation is converting the input data from a floating point to an integer value. 
     
     
         26 . The system of  claim 20 , wherein the convertor engine is configured to set a value of the output result to zero if a value of the output result is a denormal number. 
     
     
         27 . The system of  claim 20 , wherein the convertor engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity. 
     
     
         28 . The system of  claim 20 , wherein the convertor engine is configured to set a value of the output result to a minimum supported number if a value of the output result is a negative infinity. 
     
     
         29 . The system of  claim 20 , wherein the logic engine is configured to raise an out-of-bound flag if the output result is a positive infinity, a negative infinity, or a denormal number. 
     
     
         30 . The system of  claim 20 , wherein the logic engine is configured to raise a divide-by-zero flag when the floating point arithmetic operation is a division and wherein a dividend is a nonzero number and divisor is a zero number. 
     
     
         31 . A system comprising:
 a means for receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data to generate an output result;   a means for determining whether the output result is going to cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data; and   a means for converting a value of the output result to a modified value responsive to determining that the output result is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data.   
     
     
         32 . The system of  claim 31  further comprising a means for raising an out-of-bound flag if the output result is a positive infinity, a negative infinity, or a denormal number. 
     
     
         33 . The system of  claim 31  further comprising a means for raising a divide-by-zero flag when the floating point arithmetic operation is a division and wherein a dividend is a nonzero number and divisor is a zero number.