System and method for handling floating point hardware exception

Abstract

A method includes receiving a first input data and a second input data at a floating point arithmetic operating unit, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data. The method further includes determining whether the first input data is a qnan (quiet not-a-number) or whether the first input data is an snan (signaling not-a-number) prior to performing the floating point arithmetic operation. A value of the first input data is modified prior to performing the floating point arithmetic operation if the first input data is either qnan or snan, wherein the converting eliminates special handling associated with the floating point arithmetic operation on the first input data being either qnan or snan.

What is claimed is: 
     
         1 . A computer-implemented method comprising:
 receiving a first input data and a second input data at a floating point arithmetic operating unit, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, wherein the floating point operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data;   determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; and   converting a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan.   
     
     
         2 . The method of  claim 1  further comprising performing the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result. 
     
     
         3 . The method of  claim 1 , wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation. 
     
     
         4 . The method of  claim 2  further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception. 
     
     
         5 . The method of  claim 4  further comprising setting a value of the output result to zero if a value of the output result is a denormal number. 
     
     
         6 . The method of  claim 4  further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity. 
     
     
         7 . The method of  claim 1 , wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the qnan. 
     
     
         8 . The method of  claim 7  further comprising generating an un-initialized flag associated with the first input data being the qnan. 
     
     
         9 . The method of  claim 1 , wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the snan. 
     
     
         10 . The method of  claim 9  further comprising generating an un-initialized flag associated with the first input data being the snan. 
     
     
         11 . A computer-implemented method comprising:
 receiving a first input data and a second input data at a floating point arithmetic operating unit, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data;   determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; and   setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation.   
     
     
         12 . The method of  claim 11  further comprising performing the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result. 
     
     
         13 . The method of  claim 11 , wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation. 
     
     
         14 . The method of  claim 12  further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception. 
     
     
         15 . The method of  claim 14  further comprising setting a value of the output result to zero if a value of the output result is a denormal number. 
     
     
         16 . The method of  claim 14  further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity. 
     
     
         17 . The method of  claim 11  further comprising generating an un-initialized flag associated with the first input data being the qnan or snan. 
     
     
         18 . A system comprising:
 a logic engine configured to
 receive a first input data and a second input data at a floating point arithmetic operating unit, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data, 
 determine whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; and 
   a convertor engine configured to convert a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, wherein the converting eliminates special handling by the floating point arithmetic operating unit on the first input data being either the qnan or the snan.   
     
     
         19 . The system of  claim 18  further comprising said arithmetic floating point operating unit configured to perform the floating point arithmetic operation on the first input data that has been modified and on the second input data to generate an output result. 
     
     
         20 . The system of  claim 18 , wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation. 
     
     
         21 . The system of  claim 19 , wherein the logic engine is configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception. 
     
     
         22 . The system of  claim 21 , wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number. 
     
     
         23 . The system of  claim 21 , wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity. 
     
     
         24 . The system of  claim 18 , wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the qnan. 
     
     
         25 . The system of  claim 24 , wherein the logic engine is configured to generate an un-initialized flag associated with the first input data being qnan. 
     
     
         26 . The system of  claim 18 , wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the snan. 
     
     
         27 . The system of  claim 26 , wherein the logic engine is configured to generate an un-initialized flag associated with the input data being snan. 
     
     
         28 . A system comprising:
 a means for receiving a first input data and a second input data at a floating point arithmetic operating unit, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data;   a means for determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; and   a means for setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation.   
     
     
         29 . The system of  claim 28  further comprising a means for performing the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result. 
     
     
         30 . The system of  claim 29  further comprising a means for determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception. 
     
     
         31 . The system of  claim 30  further comprising a means for setting a value of the output result to zero if a value of the output result is a denormal number. 
     
     
         32 . The system of  claim 30  further comprising a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity. 
     
     
         33 . The system of  claim 28  further comprising a means for generating an un-initialized flag associated with the first input data being the qnan or snan.