System and method for handling floating point hardware exception

Abstract

A method includes receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data. The method also includes determining whether the received input data is positive infinity or negative infinity prior to performing the floating point arithmetic operation. The method further includes converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is positive infinity or negative infinity.

What is claimed is: 
     
         1 . A computer-implemented method comprising:
 receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;   determining whether the received input data is positive infinity or negative infinity prior to performing the floating point arithmetic operation; and   converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is positive infinity or negative infinity.   
     
     
         2 . The method of  claim 1  further comprising performing the floating point arithmetic operation on the input data with the modified value to generate an output result. 
     
     
         3 . The method of  claim 2  further comprising determining whether the output result of the floating point arithmetic operation causes a floating point hardware exception. 
     
     
         4 . The method of  claim 2  further comprising setting a value of the output result to zero if the value of the output result is a denormal number. 
     
     
         5 . The method of  claim 2  further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity. 
     
     
         6 . The method of  claim 1 , wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, an addition operation, a subtraction operation, a multiplication operation, a divisional operation, a max-reduce operation, a min-reduced operation, a negate operation, converting a first floating point to a second floating point if the input data is greater than a number and concerting a third floating point to a fourth floating point if the input data is less than the number, or a floating point to integer operation. 
     
     
         7 . The method of  claim 1  further comprising setting the value of the input data to zero if the input data is a denormal number. 
     
     
         8 . The method of  claim 7  further comprising generating an out-of-bounds flag associated with the denormal number. 
     
     
         9 . The method of  claim 1  further comprising generating an out-of-bounds flag associated with the input data being either positive infinity or negative infinity. 
     
     
         10 . The method of  claim 1  further comprising setting the value of the input data to zero if the input data is a quiet not-a-number (qnan). 
     
     
         11 . The method of  claim 10  further comprising generating an un-initialized flag associated with the input data being the qnan. 
     
     
         12 . The method of  claim 1 , wherein the input data is a signaling not-a-number (snan) and wherein the modified value is zero. 
     
     
         13 . The method of  claim 12  further comprising generating an un-initialized flag associated with the input data being the snan. 
     
     
         14 . A system comprising:
 a logic engine configured to
 receive an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data, 
 determine whether the received input data is positive infinity or negative infinity prior to performing the floating point arithmetic operation; and 
   a convertor engine configured to convert a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is positive infinity or negative infinity.   
     
     
         15 . The system of  claim 14  further comprising an arithmetic floating point operator configured to perform the floating point arithmetic operation on the input data with the modified value to generate an output result. 
     
     
         16 . The system of  claim 15 , wherein the logic engine is further configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception. 
     
     
         17 . The system of  claim 15 , wherein the convertor engine is further configured to set a value of the output result to zero if a value of the output result is a denormal number. 
     
     
         18 . The system of  claim 15 , wherein the convertor engine is further configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and wherein the convertor engine is further configured to set a value of the output result to a minimum supported number if a value of the output result is a negative infinity. 
     
     
         19 . The system of  claim 14 , wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, an addition operation, a subtraction operation, a multiplication operation, a divisional operation, a max-reduce operation, a min-reduced operation, a negate operation, converting a first floating point to a second floating point if the input data is greater than a number and concerting a third floating point to a fourth floating point if the input data is less than the number, or a floating point to integer operation. 
     
     
         20 . The system of  claim 14 , wherein the convertor engine is further configured to set the value of the input data to zero if the input data is a denormal number. 
     
     
         21 . The system of  claim 20 , wherein the logic engine is further configured to generate an out-of-bounds flag associated with the denormal number. 
     
     
         22 . The system of  claim 14 , wherein the convertor engine is further configured to generate an out-of-bounds flag associated with the input data being positive infinity or negative infinity. 
     
     
         23 . The system of  claim 14 , wherein the convertor engine is further configured to set the value of the input data to zero if the input data is a quiet not-a-number (qnan). 
     
     
         24 . The system of  claim 23 , wherein the logic engine is further configured to generate an un-initialized flag associated with the input data being the qnan. 
     
     
         25 . The system of  claim 14 , wherein the input data is a signaling not-a-number (snan) and wherein the modified value is zero. 
     
     
         26 . The system of  claim 25 , wherein the logic engine is configured to generate an un-initialized flag associated with the input data being the snan. 
     
     
         27 . A system comprising:
 a means for receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;   a means for determining whether the received input data is positive infinity or negative infinity prior to performing the floating point arithmetic operation; and   a means for converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is positive infinity or negative infinity.   
     
     
         28 . The system of  claim 27  further comprising a means for performing the floating point arithmetic operation on the input data with the modified value to generate an output result. 
     
     
         29 . The system of  claim 28  further comprising a means for determining whether the output result of the floating point arithmetic operation causes a floating point hardware exception. 
     
     
         30 . The system of  claim 28  further comprising a means for setting a value of the output result to zero if the value of the output result is a denormal number. 
     
     
         31 . The system of  claim 28  further comprising a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity. 
     
     
         32 . The system of  claim 27  further comprising a means for setting the value of the input data to zero if the input data is a denormal number. 
     
     
         33 . The system of  claim 32  further comprising a means for generating an out-of-bounds flag associated with the denormal number. 
     
     
         34 . The system of  claim 27  further comprising a means for generating an out-of-bounds flag associated with the input data being either positive infinity or negative infinity. 
     
     
         35 . The system of  claim 27  further comprising a means for setting the value of the input data to zero if the input data is a quiet not-a-number (qnan). 
     
     
         36 . The system of  claim 35  further comprising a means for generating an un-initialized flag associated with the input data being the qnan. 
     
     
         37 . The system of  claim 27  further comprising a means for generating an un-initialized flag associated with the input data being a signaling not-a-number (snan) and wherein the modified value is zero.