Hardening branch hardware against speculation vulnerabilities

Abstract

Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and branch circuitry coupled to the decode circuitry. The decode circuitry is to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack. The branch circuitry is to be hardened in response to the branch hardening instruction.

1 . An apparatus comprising:
 decode circuitry to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack; and   branch circuitry, coupled to the decode circuitry, to be hardened in response to the branch hardening instruction.   
     
     
         2 . The apparatus of  claim 1 , wherein the branch circuitry is to be hardened to prevent a speculative branch from being taken. 
     
     
         3 . The apparatus of  claim 1 , wherein the branch circuitry is to be hardened to prevent branch prediction. 
     
     
         4 . The apparatus of  claim 1 , wherein the branch circuitry is to be hardened to mispredict a branch to a safe location. 
     
     
         5 . The apparatus of  claim 1 , wherein the branch circuitry is to be hardened to harden a load operation in the shadow of a branch. 
     
     
         6 . The apparatus of  claim 1 , wherein the branch circuitry is to be hardened to delay a branch. 
     
     
         7 . The apparatus of  claim 6 , wherein the branch is to be delayed until a branch condition is resolved. 
     
     
         8 . The apparatus of  claim 6 , wherein the branch is to be delayed until a corresponding branch instruction is retired. 
     
     
         9 . The apparatus of  claim 6 , wherein the branch is to be delayed until a branch termination instruction is received. 
     
     
         10 . The apparatus of  claim 6 , wherein the branch is to be delayed until the branch is known to be safe. 
     
     
         11 . A method comprising:
 decoding, by a processor, a branch hardening instruction to mitigate vulnerability to a speculative execution attack; and   hardening, in response to the branch hardening instruction, branch circuitry in the processor.   
     
     
         12 . The method of  claim 11 , wherein hardening the branch circuitry includes preventing a speculative branch from being taken. 
     
     
         13 . The method of  claim 11 , wherein hardening the branch circuitry includes preventing branch prediction. 
     
     
         14 . The method of  claim 11 , wherein hardening the branch circuitry includes mispredicting a branch to a safe location. 
     
     
         15 . The method of  claim 11 , wherein hardening the branch circuitry includes hardening a load operation in the shadow of a branch. 
     
     
         16 . The method of  claim 11 , wherein hardening the branch circuitry includes delaying a branch. 
     
     
         17 . The method of  claim 16 , wherein the branch is delayed until a branch condition is resolved. 
     
     
         18 . The method of  claim 16 , wherein the branch is delayed until a corresponding branch instruction is retired. 
     
     
         19 . A non-transitory machine-readable medium storing a plurality of instructions, including a branch hardening instruction and a branch instruction, wherein execution of the plurality of instructions by a machine causes the machine to perform a method comprising:
 hardening branch circuitry in the machine in response to the branch hardening instruction;   delaying a branch to be taken in response to the branch instruction;   retiring the branch instruction; and   relaxing hardening of the branch circuitry in response to retiring the branch instruction.   
     
     
         20 . The non-transitory machine-readable medium of  claim 19 , wherein the plurality of instructions includes a branch condition resolution instruction, the branch condition resolution instruction is to resolve a branch condition, and delaying the branch continues until the branch condition is resolved.