Quantum cascade laser devices with improved heat extraction

Abstract

Structures and methods for reducing the thermal resistance of quantum cascade laser (QCL) devices and QCL-based photonic integrated circuits (QCL-PIC) are provided. In various embodiments, the native substrate of QCL and QCL-PIC devices is replaced with a foreign substrate that has very high thermal conductivity, for example, using wafer bonding methods. In some examples, wafer bonding of processed, semi-processed, or unprocessed QCL and QCL-PIC epilayers or devices on their native substrate to a high-thermal-conductivity substrate is performed, followed by removal of the native substrate via selective etching, and performing additional device processing if necessary. Thereafter, in some embodiments, cleaving or dicing individual devices from the bonded wafers may be performed, for example, for mounting onto heat sinks.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor device, comprising:
 providing a wafer including a native substrate and a plurality of epitaxial layers (epilayers) disposed over the native substrate, wherein the plurality of epilayers includes a quantum cascade laser (QCL) active region;   performing a wafer-level epilayer-down bonding of the wafer to a foreign substrate having a thermal conductivity greater than that of silicon (Si), wherein the wafer-level epilayer-down bonding includes bonding a top epilayer of the plurality of epilayers face-down onto a top surface of the foreign substrate; and   after performing the wafer-level epilayer-down bonding, removing the native substrate from the wafer, while the plurality of epilayers remains bonded to the foreign substrate.   
     
     
         2 . The method of  claim 1 , wherein the plurality of epilayers includes a passive waveguide heterostructure for fabrication of QCL photonic integrated circuits. 
     
     
         3 . The method of  claim 1 , wherein the foreign substrate includes at least one of SiC, AlN, diamond, and BeO. 
     
     
         4 . The method of  claim 1 , wherein the foreign substrate has a thermal expansion coefficient within about +/−10% of that of the native substrate. 
     
     
         5 . The method of  claim 1 , wherein the plurality of epilayers include unprocessed, semi-processed, or fully-processed QCL epilayers. 
     
     
         6 . The method of  claim 5 , further comprising after removing the native substrate from the wafer, performing additional processing to the plurality of epilayers when the plurality of epilayers includes unprocessed or semi-processed QCL epilayers. 
     
     
         7 . The method of  claim 1 , further comprising:
 after removing the native substrate from the wafer, using the plurality of epilayers to complete fabrication of a QCL device bonded to the foreign substrate; and   dicing the QCL device bonded to the foreign substrate for mounting onto a heat sink.   
     
     
         8 . The method of  claim 1 , wherein the native substrate includes an indium phosphide (InP) substrate. 
     
     
         9 . The method of  claim 1 , wherein the performing the wafer-level epilayer-down bonding of the wafer to the foreign substrate includes performing a thermo-compression metal-metal bonding process. 
     
     
         10 . The method of  claim 9 , wherein prior to performing the thermo-compression metal-metal bonding process, depositing a bonding material layer onto at least one of the top epilayer of the plurality of epilayers and the top surface of the foreign substrate. 
     
     
         11 . The method of  claim 10 , wherein the bonding material layer includes gold (Au) or a Au-containing material layer. 
     
     
         12 . The method of  claim 1 , wherein the providing the wafer further includes providing an etch stop layer disposed between the native substrate and the plurality of epilayers, and wherein the etch stop layer is removed after removing the native substrate. 
     
     
         13 . A method, comprising:
 providing a first substrate including an at least partially processed quantum cascade laser (QCL) device disposed on a first side of the first substrate;   attaching the first substrate including the QCL device with the first side of the first substrate face-down onto a carrier wafer using an adhesive layer;   after attaching the first substrate onto the carrier wafer, removing the first substrate using a selective etchant to expose a back side of the at least partially processed QCL device that remains bonded to the carrier wafer;   after removing the first substrate, performing a thermo-compression metal-metal bonding process, along the exposed back side of the at least partially processed QCL device, to bond the at least partially processed QCL device to a second substrate having a thermal conductivity greater than that of silicon (Si); and   after performing the thermo-compression metal-metal bonding process, removing the adhesive layer to detach the carrier wafer from the at least partially processed QCL device.   
     
     
         14 . The method of  claim 13 , wherein the second substrate includes at least one of SiC, AlN, diamond, and BeO. 
     
     
         15 . The method of  claim 13 , wherein the second substrate has a thermal expansion coefficient within about +/−10% of that of the first substrate. 
     
     
         16 . The method of  claim 13 , further comprising:
 after removing the adhesive layer, performing further processing of the at least partially processed QCL device to form a completed QCL device bonded to the second substrate; and   dicing the completed QCL device bonded to the second substrate for mounting onto a heat sink.   
     
     
         17 . The method of  claim 13 , wherein the first substrate includes an indium phosphide (InP) substrate. 
     
     
         18 . The method of  claim 13 , wherein the first substrate includes a QCL photonic integrated circuit including a QCL heterostructure and a passive waveguide heterostructure. 
     
     
         19 . The method of  claim 13 , wherein prior to performing the thermo-compression metal-metal bonding process, depositing a metal bonding material layer onto at least one of the exposed back side of the at least partially processed QCL device and a top surface of the second substrate. 
     
     
         20 . The method of  claim 19 , wherein the metal bonding material layer includes gold (Au) or a Au-containing material layer. 
     
     
         21 . A semiconductor device, comprising:
 a thermally conductive substrate having a thermal conductivity equal to or greater than that of silicon (Si);   a semiconductor heterostructure disposed over the thermally conductive substrate, wherein the semiconductor heterostructure includes a lower cladding layer, a quantum cascade laser (QCL) active region, and an upper cladding layer; and   a thermo-compression metal-metal bond that bonds the thermally conductive substrate to the semiconductor heterostructure.   
     
     
         22 . The semiconductor device of  claim 21 , further comprising a first contact and a second contact coupled for current injection through the semiconductor heterostructure. 
     
     
         23 . The semiconductor device of  claim 22 , wherein the thermally conductive substrate is also electrically conductive, and wherein the first contact and the second contact are coupled for top-bottom current injection through the semiconductor heterostructure and through the thermally and electrically conductive substrate. 
     
     
         24 . The semiconductor device of  claim 21 , further comprising a dielectric layer disposed on opposing sidewalls of the semiconductor heterostructure. 
     
     
         25 . The semiconductor device of  claim 21 , further comprising a heat sink bonded to a back side of the thermally conductive substrate by a bonding solder. 
     
     
         26 . The semiconductor device of  claim 21 , wherein the semiconductor heterostructure further includes a passive waveguide heterostructure for fabrication of QCL photonic integrated circuits.