System and method for retaining dram data when reprogramming reconfigureable devices with dram memory controllers incorporating a data maintenance block

Abstract

A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.

1 . An apparatus comprising:
 a reconfigurable logic device having a memory controller operable to be coupled to inputs and outputs of a DRAM memory; and   a data maintenance block operable to be coupled to self-refresh command inputs of said DRAM memory, said data maintenance block operative to provide stable input levels on said self-refresh command inputs while said reconfigurable logic device is reconfigured, wherein said memory controller is located within a portion of said reconfigurable logic device which is subject to being reconfigured.   
     
     
         2 . The apparatus of  claim 1  wherein said reconfigurable logic device comprises an FPGA. 
     
     
         3 . The apparatus of  claim 1  wherein said reconfigurable logic device comprises said data maintenance block, wherein said data maintenance block is located within a portion of said reconfigurable logic device which is not subject to being reconfigured. 
     
     
         4 . The apparatus of  claim 3  wherein said reconfigurable logic device comprises an FPGA. 
     
     
         5 . The apparatus of  claim 1  wherein said data maintenance block is external to said reconfigurable logic device. 
     
     
         6 . The apparatus of  claim 4  wherein said DRAM memory comprises DDR3 compliant memory devices. 
     
     
         7 . The computer system of  claim 4  wherein said DRAM memory comprises DDR4 compliant memory devices. 
     
     
         8 . The apparatus of  claim 5  wherein said DRAM memory comprises DDR3 compliant memory devices. 
     
     
         9 . The computer system of  claim 5  wherein said DRAM memory comprises DDR4 compliant memory devices.