Hyperscale switch and method for data packet network switching

Abstract

A hyperscale switch is implemented with a plurality of semiconductor crossbar switching elements connected to one another according to a direct point-to-point electrical mesh interconnect for transceiving data packets between peripheral devices connected to the switch and utilizing a lookup table and network device addressing for reduced switching power.

What is claimed is: 
     
         1 . A non-Clos network data packet switch comprising:
 a plurality of semiconductor crossbar switch elements connected to one another according to a direct point-to-point electrical mesh interconnect;   wherein data packets from a first peripheral device connected to one of said semiconductor crossbar switch elements are communicated to a second peripheral device connected to another one of said semiconductor crossbar switch elements via said direct point-to-point electrical mesh interconnect according to a lookup table and network device addressing for reduced switching power.   
     
     
         2 . The switch of  claim 1 , wherein the lookup table includes a mapping of peripheral device connections with corresponding I/O ports associated with said plurality of semiconductor switch elements according to the point to point connectivity of the electrical mesh interconnect to corresponding I/O ports of each semiconductor switch element. 
     
     
         3 . The switch of  claim 2 , wherein a destination semiconductor crossbar switch element and destination I/O port is determined according to the lookup table mapping using said data indicative of the destination address as an index to the lookup table. 
     
     
         4 . The switch according to  claim 1 , wherein each of the plurality of semiconductor switch elements includes a control plane having a processor and memory in communication with a master controller and address routing table for receiving routing table entries and updates for transfer into each of the semiconductor switch elements. 
     
     
         5 . The switch of  claim 1 , wherein each of said plurality of semiconductor switch elements includes at least one field programmable gate array (FPGA). 
     
     
         6 . The switch of  claim 1 , wherein the point-to-point electrical mesh interconnect is comprised of at least one multi-layer stack of electrically interconnected printed circuit boards. 
     
     
         7 . The switch of  claim 6 , wherein the at least one multi-layer stack of electrically interconnected printed circuit boards is silicon-free. 
     
     
         8 . The switch of  claim 1 , wherein said data packets comprise header information including data indicative of a source address of the source peripheral device and of a destination address of the destination peripheral device. 
     
     
         9 . The switch of  claim 8 , wherein the header information includes one of a MAC address and an IP address, and wherein the lookup table stores one of MAC addresses and IP addresses corresponding to connected peripheral devices. 
     
     
         10 . The switch of  claim 1 , wherein one or more of said semiconductor switch elements is configurable for one of 10 Gb, 25 Gb, 40 Gb, 50 Gb, and 100 Gb signal line processing. 
     
     
         11 . A method of communicating data packets in a non-Clos data packet switching network, comprising:
 connecting a plurality of semiconductor crossbar switch elements to one another according to a direct point-to-point electrical mesh interconnect; and   transferring data packets from a first peripheral device connected to one of said semiconductor crossbar switch elements to a second peripheral device connected to another one of said semiconductor crossbar switch elements via said direct point-to-point electrical mesh interconnect, according to a lookup table and network device addressing;   wherein said lookup table includes mapping of each of the plurality of semiconductor switch elements I/O ports to another one of said plurality of semiconductor switch elements I/O ports, according to the point to point connectivity of the electrical mesh interconnect.   
     
     
         12 . The method of  claim 11 , wherein said mapping of values in said lookup table is performed according to a hash function. 
     
     
         13 . The method of  claim 11 , wherein the data packets are transferred from the first peripheral to the second peripheral device by said first semiconductor crossbar switch element prepending an indicator of the destination I/O port of the second semiconductor crossbar switch element and outputting the data packet and said indicator onto said direct point-to-point electrical mesh interconnect for transfer to said second semiconductor crossbar switch element. 
     
     
         14 . The method of  claim 13 , further comprising discarding header data prior to said output of the data packet onto the second semiconductor switch element destination I/O port identified. 
     
     
         15 . The method of  claim 11 , further comprising diverting packets to a buffer for subsequent processing when said packets cannot be forwarded due to contention within one of said semiconductor switch elements. 
     
     
         16 . The method of  claim 11 , further comprising, on the condition that a device address is not in the lookup table, forwarding said device address for updating into a master table.