Methods and apparatuses to form self-aligned caps

Abstract

At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

1 . A method to manufacture an electronic device, comprising:
 providing a substrate having a plurality of electronic devices formed thereon;   depositing a dielectric layer on the substrate;   etching trenches within the dielectric layer;   depositing a barrier layer into the trenches;   depositing a conductive material comprising copper upon the barrier layer in the trenches, so as to fill the trenches with the conductive material comprising copper;   chemical-mechanical polishing (CMP) the copper from the regions on top of the dielectric layer outside of the trenches so as to form a planer surface, thereby forming conductive lines comprising copper within the trenches;   recessing the conductive material within the trenches using an isotropic etch;   selectively depositing a capping layer comprising cobalt on the recessed conductive material within the trenches; and   controlling deposition of the capping layer, such that deposition of the capping layer is terminated such that the capping layer is contained within the trenches.   
     
     
         2 . The method of  claim 1 , wherein recessing the conductive material within the trenches comprises:
 etching the conductive material for a predetermined etching time using an etching chemistry that includes an etchant, an oxidizer, an inhibitor and a solvent.   
     
     
         3 . The method of  claim 2 , wherein the etching chemistry includes:
 between about 0.1% to about 70% by mass of an etchant;   between about 0.1% to about 10% by mass of an oxidizer;   between about 50 ppm to about 1% by mass of an inhibitor; and   between about 1% to about 60% by mass of a solvent.   
     
     
         4 . The method of  claim 2 , wherein the predetermined etching time is a time in which the etch recesses the conductive material within the trenches by a predetermined amount. 
     
     
         5 . The method of  claim 2 , wherein controlling deposition of the capping layer includes:
 depositing the capping layer for a predetermined deposition time, during which the capping layer is selectively deposited on the recessed conductive material within the trenches.   
     
     
         6 . The method of  claim 1 , wherein the barrier layer comprises cobalt. 
     
     
         7 . The method of  claim 1 , wherein the barrier layer comprises titanium nitride (TiN). 
     
     
         8 . The method of  claim 1 , wherein the dielectric layer comprises carbon. 
     
     
         9 . The method of  claim 1 , wherein selectively depositing the capping layer on the recessed conductive material within the trenches is performed in a manner that results in no deposition of the capping layer on top of the dielectric layer outside of the trenches. 
     
     
         10 . The method of  claim 1 , further comprising:
 depositing a conductive seed layer onto the barrier layer, the conductive seed layer configured to facilitate nucleation of the conductive material subsequently deposited thereon.   
     
     
         11 . An electronic device comprising:
 a substrate having a plurality of electronic devices formed thereon;   a dielectric layer deposited on the substrate;   trenches etched within the dielectric layer;   a barrier layer deposited into the trenches;   a conductive material comprising copper deposited upon the barrier layer in the trenches, so as to fill the trenches with the conductive material comprising copper;
 wherein the regions on top of the dielectric layer outside of the trenches have the conductive material removed by chemical-mechanical polishing (CMP); 
 wherein the conductive material within the trenches is recessed using an etch; and 
   a capping layer comprising cobalt selectively deposited on the recessed conductive material within the trenches,
 wherein deposition of the capping layer is controlled, such that deposition of the capping layer is terminated such that the capping layer is contained within the trenches. 
   
     
     
         12 . The electronic device of  claim 11 , wherein recessing the conductive material within the trenches comprises:
 etching the conductive material for a predetermined etching time using an etching chemistry that includes an etchant, an oxidizer, an inhibitor and a solvent.   
     
     
         13 . The electronic device of  claim 12 , wherein the etching chemistry includes:
 between about 0.1% to about 70% by mass of an etchant;   between about 0.1% to about 10% by mass of an oxidizer;   between about 50 ppm to about 1% by mass of an inhibitor; and   between about 1% to about 60% by mass of a solvent.   
     
     
         14 . The electronic device of  claim 12 , wherein the predetermined etching time is a time in which the etch recesses the conductive material within the trenches by a predetermined amount. 
     
     
         15 . The electronic device of  claim 12 , wherein controlling deposition of the capping layer includes:
 controlling a predetermined deposition time, during which the capping layer is selectively deposited on the recessed conductive material within the trenches.   
     
     
         16 . The electronic device of  claim 11 , wherein the barrier layer comprises cobalt. 
     
     
         17 . The electronic device of  claim 11 , wherein the barrier layer comprised titanium nitride (TiN). 
     
     
         18 . The electronic device of  claim 11 , wherein the dielectric layer comprises carbon. 
     
     
         19 . The electronic device of  claim 11 , wherein selectively depositing the capping layer on the recessed conductor within the trenches is performed is a manner that results in no deposition of the capping layer on top of the dielectric layer outside of the trenches. 
     
     
         20 . The electronic device of  claim 11 , further comprising:
 a conductive seed layer deposited onto the barrier layer, the conductive seed layer configured to facilitate nucleation of the conductive material subsequently deposited thereon.