Resistive memory architectures with multiple memory cells per access device

Abstract

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

What is claimed is: 
     
         1 . A method, comprising:
 generating, at a memory device comprising at least a first memory cell, a cell select signal;   transmitting, via a first rectifying device coupled with a cell select line, the cell select signal to the first memory cell; and   activating the first memory cell based at least in part on transmitting the cell select signal to the first memory cell.   
     
     
         2 . The method of  claim 1 , wherein transmitting the cell select signal to the first memory cell comprises:
 passing, by the first rectifying device, the cell select signal to the first memory cell.   
     
     
         3 . The method of  claim 1 , further comprising:
 maintaining a second memory cell of the memory device in a disabled state based at least in part on activating the first memory cell, wherein the second memory cell is coupled with a second rectifying device coupled with a second cell select line.   
     
     
         4 . The method of  claim 1 , further comprising:
 reading first data from the first memory cell based at least in part on activating the first memory cell, wherein reading the first data from the first memory cell comprises passing a first current through the first memory cell.   
     
     
         5 . The method of  claim 4 , further comprising:
 determining a logic state associated with the first data read from the first memory cell, wherein determining the logic state associated with the first data read from the first memory cell comprises measuring, by a sense amplifier, the first current passed through the first memory cell.   
     
     
         6 . The method of  claim 1 , further comprising:
 writing data to the first memory cell based at least in part on activating the first memory cell, wherein writing the data to the first memory cell comprises generating a voltage differential between the cell select line and a digit line coupled with the first memory cell.   
     
     
         7 . The method of  claim 6 , wherein generating the voltage differential between the cell select line and the digit line coupled with the first memory cell comprises:
 altering a voltage of the cell select line, altering a voltage of the digit line coupled with the first memory cell, or a combination thereof.   
     
     
         8 . The method of  claim 1 , wherein the first memory cell is coupled with the cell select line and an access device via the first rectifying device, wherein the access device is coupled with a third memory cell. 
     
     
         9 . The method of  claim 8 , wherein the access device provides shared access to at least the first memory cell and the third memory cell. 
     
     
         10 . The method of  claim 1 , wherein at least the first memory cell comprises a phase change memory cell. 
     
     
         11 . The method of  claim 1 , wherein at least the first memory cell comprises a resistive memory cell. 
     
     
         12 . The method of  claim 1 , wherein the first rectifying device comprises a diode. 
     
     
         13 . A method, comprising:
 transmitting, via a common electrode positioned between a first memory cell and a second memory cell of a memory device, a cell select signal to the first memory cell;   coupling, by the common electrode, the first memory cell and the second memory cell with a cell select line;   receiving, by at least the first memory cell, the cell select signal via the common electrode; and   activating the first memory cell based at least in part on receiving the cell select signal via the common electrode.   
     
     
         14 . The method of  claim 13 , wherein receiving the cell select signal via the common electrode comprises:
 passing, by a first rectifying device coupled with the first memory cell, the cell select signal to the first memory cell.   
     
     
         15 . The method of  claim 13 , further comprising:
 maintaining the second memory cell of the memory device in a disabled state based at least in part on activating the first memory cell, wherein the second memory cell is coupled with a second rectifying device coupled with a second cell select line.   
     
     
         16 . The method of  claim 13 , further comprising:
 activating the cell select line and an access device coupled with the first memory cell, wherein transmitting the cell select signal to the first memory cell is based at least in part on activating the cell select line and the access device coupled with the first memory cell.   
     
     
         17 . The method of  claim 13 , wherein the first memory cell and the second memory cell comprise phase change memory cells. 
     
     
         18 . The method of  claim 13 , wherein the first memory cell and the second memory cell comprise resistive memory cells. 
     
     
         19 . A method, comprising:
 generating, at a memory device comprising at least a first memory cell, a cell select signal;   transmitting, via a first diode coupled with a cell select line, the cell select signal to the first memory cell;   activating the first memory cell based at least in part on transmitting the cell select signal to the first memory cell; and   performing an access operation on the first memory cell based at least in part on activating the first memory cell.   
     
     
         20 . The method of  claim 19 , wherein a first voltage is applied to the cell select line based at least in part on transmitting the cell select signal to the first memory cell, wherein performing the access operation on the first memory cell comprises:
 adjusting the first voltage of the cell select line from the first voltage to a second voltage; and   
       writing data to the first memory cell based at least in part on adjusting the first voltage of the cell select line from the first voltage to the second voltage.