Systems and methods for an intelligent mapping of neural network weights and input data to an array of processing cores of an integrated circuit

Abstract

Systems and methods of configuring an array of processors of an integrated circuit includes identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data includes a bit-reversed input array, configuring the array of processing cores based on the bit-reversed input array, wherein the configuring the array of processing cores includes storing the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array, and performing matrix multiply computations between weight stages of the FFT matrix multiply and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.

What is claimed: 
     
         1 . A method of transforming input data on an integrated circuit, the method comprising:
 implementing a signal conversion of input data for processing on an integrated circuit;   generating a transformation matrix multiply based on implementing the signal conversion of the input data, the transformation matrix multiply comprising:
 (1) a bit-reversed input array comprising N-bits of input, where N is a number of input bits in the bit-reversed input array; and 
 (2) a plurality of weight stages, wherein each weight stage of the plurality of weight stages comprises a distinct weight matrix; 
   storing one or more of the input bits of the bit-reversed input array within memory circuits of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location of each input bit of the bit-reversed input array; and   executing the transformation matrix multiply including performing a plurality of matrix multiply computations between the plurality of weight stages and the input bits of the bit-reversed input array stored within the memory circuits.   
     
     
         2 . A method of configuring an integrated circuit for processing data, the method comprising:
 identifying a transformation matrix multiply of input data, wherein the transformation matrix multiply of the input data comprises a bit-reversed input array;   configuring the integrated circuit based on the bit-reversed input array, wherein the configuring the integrated circuit includes:
 storing one or more of the input bits of the bit-reversed input array within memory circuits of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location of each input bit of the bit-reversed input array within distinct memory circuits of the integrated circuit; and 
   executing by the integrated circuit the transformation matrix multiply including performing a plurality of matrix multiply computations between a plurality of weight stages of the transformation matrix multiply and the input bits of the bit-reversed input array.