Boost schemes for write assist

Abstract

A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.

What is claimed is: 
     
         1 . A write assist circuit comprising:
 a first transistor switch connected between a word line voltage node and a supply voltage, wherein a gate of the first transistor switch is operative to receive a boost signal responsive to a write enable signal;   a second transistor switch connected between the word line voltage node and the supply voltage, wherein a gate of the second transistor switch is coupled to the word line voltage node; and   a metal capacitor having a first end coupled to the word line voltage node and a second end operative to receive the boost signal, wherein the metal capacitor is operative to drive a word line voltage of the word line voltage node to a boosted value from the supply voltage in response to the boost signal.   
     
     
         2 . The write assist circuit of  claim 1 , wherein the boost signal is operative to turn off the first transistor switch, initiate charging of the metal capacitor, and boost the word line voltage. 
     
     
         3 . The write assist circuit of  claim 1 , further comprising a word line driver circuit operative to provide the word line voltage to a word line of a cell array. 
     
     
         4 . The write assist circuit of  claim 1 , further comprising a metal oxide semiconductor connected in parallel to the metal capacitor. 
     
     
         5 . The write assist circuit of  claim 1 , wherein the metal capacitor is a hand clasping style metal capacitor comprising a first plurality of metal stripes and a second plurality of metal stripes. 
     
     
         6 . The write assist circuit of  claim 5 , wherein a length of at least one of the first plurality of metal stripes and the second plurality of metal stripes comprises a base length and an extended length, wherein the extended length is less than or equal to a word line length of a cell array. 
     
     
         7 . The write assist circuit of  claim 5 , wherein the first plurality of metal stripes are in a first metal layer and the second plurality of metal stripes are formed in a second metal layer, the second metal layer being different from the first metal layer. 
     
     
         8 . The write assist circuit of  claim 5 , wherein the first plurality of metal stripes form a first sub-capacitor and the second plurality of metal stripes form a second sub-capacitor, wherein the second sub-capacitor is parallel to the first sub-capacitor. 
     
     
         9 . The write assist circuit of  claim 8 , wherein at least one of the first sub-capacitor and the second sub-capacitor is selectively enabled. 
     
     
         10 . A write assist circuit comprising:
 a first transistor connected between a word line voltage node and a supply voltage, wherein a gate of the first transistor is operative to receive a boost signal responsive to a write enable signal;   a second transistor connected between the word line voltage node and the supply voltage, wherein a gate of the second transistor is coupled to the word line voltage node;   a third transistor connected between the word line voltage node and the supply voltage, wherein a gate of the third transistor is coupled to the word line voltage node, and wherein a source and a drain of the third transistor are connected together and are operative to receive the boost signal; and   a metal capacitor having a first end coupled to the word line voltage node and a second end operative to receive the boost signal, wherein the metal capacitor is operative to drive a word line voltage of the word line voltage node to a boosted value from the supply voltage in response to the boost signal.   
     
     
         11 . The write assist circuit of  claim 10 , further comprising a word line driver circuit operative to provide the word line voltage to a word line of a cell array. 
     
     
         12 . The method of  claim 10 , wherein the first metal capacitor is a hand clasping style metal capacitor comprising a first plurality of metal stripes and a second plurality of metal stripes. 
     
     
         13 . The method of  claim 12 , wherein a length of at least one of the first plurality of metal stripes and the second plurality of metal stripes comprises a base length and an extended length, wherein the extended length is less than or equal to a word line length of a cell array. 
     
     
         14 . The method of  claim 12 , wherein the first plurality of metal stripes are in a first metal layer and the second plurality of metal stripes are formed in a second metal layer, the second metal layer being different from the first metal layer. 
     
     
         15 . The method of  claim 12 , wherein the first plurality of metal stripes form a first sub-capacitor and the second plurality of metal stripes form a second sub-capacitor, wherein the second sub-capacitor is parallel to the first sub-capacitor. 
     
     
         16 . A write assist circuit comprising:
 a first transistor connected between a word line voltage node and a supply voltage, wherein a gate of the first transistor is operative to receive a boost signal responsive to a write enable signal;   a second transistor connected between the word line voltage node and the supply voltage, wherein a gate of the second transistor is coupled to the word line voltage node;   a third transistor connected between the word line voltage node and the supply voltage, wherein a gate of the third transistor is coupled to the word line voltage node, and wherein a source and a drain of the third transistor are connected together and are operative to receive the boost signal; and   a first metal capacitor comprising a first plurality of metal stripes substantially parallel to each other and a second plurality of metal stripes substantially parallel to each other, wherein the first plurality of metal stripes are coupled to the word line voltage node, wherein the second plurality of metal stripes are operative to receive the boost signal, wherein the metal capacitor is operative to drive a word line voltage of the word line voltage node to a boosted value from the supply voltage in response to the boost signal.   
     
     
         17 . The write assist circuit of  claim 16 , wherein the first metal capacitor is a hand clasping style metal capacitor. 
     
     
         18 . The write assist circuit of  claim 16 , wherein the first plurality of metal stripes are in a first metal layer and the second plurality of metal stripes are formed in a second metal layer, the second metal layer being different from the first metal layer. 
     
     
         19 . The write assist circuit of  claim 16 , wherein the first plurality of metal stripes form a first sub-capacitor and the second plurality of metal stripes form a second sub-capacitor, wherein the second sub-capacitor is parallel to the first sub-capacitor. 
     
     
         20 . The write assist circuit of  claim 19 , wherein at least one of the first sub-capacitor and the second sub-capacitor is selectively enabled.