Content aware scheduling in a hevc decoder operating on a multi-core processor platform

Abstract

A method is provided for decoding an encoded video stream on a processor having a plurality of processing cores includes receiving and examining a video stream to identify any macroscopic constructs present therein that support parallel processing. Decoding of the video stream is divided into a plurality of decoding functions. The plurality of decoding functions is scheduled for decoding the video stream in a dynamic manner based on availability of any macroscopic constructs that have been identified and then based on a number of bytes used to encode each block into which each picture of the video stream is partitioned. Each of the decoding functions is dispatched to the plurality of processing cores in accordance with the scheduling.

1 . A method of decoding an encoded video stream on a processor having a plurality of processing cores, comprising:
 receiving the encoded video stream;   examining the video stream to identify a plurality of macroscopic constructs present therein that support parallel processing where each of said macroscopic constructs has a different processor load, wherein a first processor load is a time taken for Context Adaptive Binary Arithmetic Coding (CABAC) processing of a part of the video stream, wherein a second processor load is a time taken for processing of a non-Context Adaptive Binary Arithmetic Coding (CABAC) process of a remaining part of the video stream;   dividing decoding of the video stream into a plurality of decoding functions;   assigning a first one of said macroscopic constructs having said first processor load corresponding to said Context Adaptive Binary Arithmetic Coding (CABAC) processing to a first core of said plurality of processing cores of said processor;   assigning a second one of said macroscopic constructs having said second processor load corresponding to said processing of said non-Context Adaptive Binary Arithmetic Coding (CABAC) process of a said remaining part of the video stream to a second core of said plurality of processing cores of said microprocessor the plurality of decoding functions for decoding the video stream in a dynamic manner based on availability of any macroscopic constructs that have been identified and the video stream is partitioned among the plurality of processing cores of said processor; and   dispatching each of the decoding functions to the respective processing cores in accordance with the assigning.   
     
     
         2 . The method of  claim 1 , wherein the assigning of the first one and the second one are based on the availability of a prioritized list of macroscopic functions. 
     
     
         3 . The method of  claim 2 , wherein the prioritized list of macroscopic functions, from highest priority to lowest priority, includes tiles, wavefronts, and slices within a picture of the video stream. 
     
     
         4 . The method of  claim 1 , wherein the video stream includes tiles and the assigning includes grouping tiles into different sets and assigning decoding of each set of tiles on a different core. 
     
     
         5 . The method of  claim 4 , wherein each set of tiles has a processor load that are as equal to one another as possible. 
     
     
         6 . The method of  claim 1 , wherein a picture of the video stream includes a number of tiles and the number of tiles is less than a number of cores that are available, and further comprising assigning decoding of each tile across at least two cores. 
     
     
         7 . The method of  claim 1 , wherein the plurality of decoding functions includes a plurality of atomic decoding functions, the plurality of atomic decoding functions including all of the plurality of decoding functions exclusive of decoding functions applicable to the macroscopic constructs, and further comprising assigning the atomic decoding functions based on the processor load used to process each of the atomic decoding functions. 
     
     
         8 . The method of  claim 7 , wherein a threshold processor load is used to assign the atomic decoding functions to be assigned to different cores.