US2022334742A1PendingUtilityA1

Cpu cache

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Assignee: KOVE IP LLCPriority: Sep 16, 2014Filed: Jul 5, 2022Published: Oct 20, 2022
Est. expirySep 16, 2034(~8.2 yrs left)· nominal 20-yr term from priority
G06F 2212/683G06F 3/067G06F 12/1027G06F 3/0632G06F 3/0604Y02D10/00
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Claims

Abstract

An apparatus may be provided in which a processor is configured to cause, in response to a first memory allocation request from an application, allocation of a region of an external primary memory on a memory appliance, the external primary memory on the memory appliance accessible by the apparatus over an interconnect with client-side memory access, wherein the processor is further configured to cache data in the local primary memory that is accessed in the external primary memory on the memory appliance, wherein the processor is further configured to: allocate, in response to a second memory allocation request from the application, a slab of the external primary memory by: a selection, at the apparatus, of a subset of the region of the external primary memory to be the slab, and a mapping, at the apparatus, of the slab of the external primary memory to a virtual address space.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A memory appliance comprising:
 a communication interface configured to communicate over a network;   a processor; and   a memory configured in an address space addressable by the processor, wherein the processor is configured to:   memory map at least a portion of a file to a memory region included in the memory, wherein a virtual address addressable by the processer is generated, and the at least a portion of file is accessible through the memory region at the virtual address; and   register the virtual address with the communication interface, wherein registration of the virtual address provides client-side memory access to the memory region, wherein the communication interface is configured to access to the memory region for a client of the memory appliance in a client-side memory access operation conforming to a memory access protocol.

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