Bias generation circuit, buffer circuit including the bias generation circuit and semiconductor system including the buffer circuit

Abstract

A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

What is claimed is: 
     
         1 . A buffer circuit comprising:
 a current mode circuit configured to generate an output signal based on a power voltage and an input signal and configured to compensate for a transition timing change of the output signal based on a level of a bias voltage; and   a bias generation circuit configured to generate the bias voltage based on a reference voltage, configured to detect a level change of the power voltage, and configured to control the level of the bias voltage based on detection results.   
     
     
         2 . The buffer circuit of  claim 1 , wherein the bias generation circuit is configured to remove a high-frequency component from the level change of the power voltage and configured to detect a low-frequency component in the level change of the power voltage. 
     
     
         3 . The buffer circuit of  claim 1 , wherein the bias generation circuit comprises:
 a bias generator configured to generate the bias voltage based on a reference voltage; and   a compensator configured to detect the level change of the power voltage and configured to control the level of the bias voltage based on the detection results.   
     
     
         4 . The buffer circuit of  claim 3 , wherein the reference voltage has a temperature proportion characteristic. 
     
     
         5 . The buffer circuit of  claim 3 , wherein the bias generator comprises:
 a comparison circuit configured to compare a feedback voltage with the reference voltage and to output comparison results; and   a voltage generation circuit configured to generate a bias voltage through a first current path and a second current path based on the output of the comparison circuit, the first current path configured to generate the feedback voltage, and the second current path formed by mirroring a current flowing through the first current path.   
     
     
         6 . The buffer circuit of  claim 3 , wherein the compensator is configured to detect a low-frequency change in the level of the power voltage and configured to control the level of the bias voltage based on the detection results. 
     
     
         7 . The buffer circuit of  claim 3 , wherein the compensator comprises:
 a voltage change tracker configured to detect the change of the power voltage;   a low pass filter configured to remove a high-frequency component from an output of the voltage change tracker to allow a low-frequency component to pass through the low pass filter; and   a bias level controller configured to control the level of the bias voltage based on an output of the low pass filter.   
     
     
         8 . The buffer circuit of  claim 3 , wherein the bias generator is activated by a first enable signal, and
 wherein the compensator is activated by a second enable signal.