US2022360647A1PendingUtilityA1

Flexible header alteration in network devices

Assignee: MARVELL ISRAEL MISL LTDPriority: Jan 29, 2019Filed: May 23, 2022Published: Nov 10, 2022
Est. expiryJan 29, 2039(~12.5 yrs left)· nominal 20-yr term from priority
H04L 49/25H04L 69/22H04L 49/9094H04L 45/74H04L 69/164H04L 49/9015H04L 47/2441H04L 69/12H04L 12/4641H04L 69/16H04L 47/6245
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Claims

Abstract

At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for processing packets in a network device, the method comprising:
 receiving, at a packet processor of the network device, a packet received by the network device from a network link;   determining, with the packet processor, at least one egress interface via which the packet is to be transmitted by the network device;   providing at least a packet header of the packet to a programmable header alteration engine of the packet processor, the programmable header alteration engine including i) a hardware input processor implemented in hardware and ii) a programmable header alteration processor coupled to a program memory, the programmable header alteration processor being configured to execute computer readable instructions stored in the program memory to perform one or more header alteration operations on received packets;   determining, with the hardware input processor of the programmable header alteration engine, whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor;   providing, with the hardware input processor of the programmable header alteration engine, the packet header to the processing path or to the bypass path based on the determination of whether the packet header is to be provided to the processing path or to be diverted to the bypass path;   selectively i) processing the packet header by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processing the packet header by the programmable header alteration processor when the packet header is provided to the bypass path; and   transmitting, with the network device, the packet via the at least one egress interface of the network device.

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