Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network

Abstract

Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming an analog neural non-volatile memory cell in an array to a target value representing one of N different values, where N is an integer; verifying that a value stored in the analog neural non-volatile memory cell is within an acceptable window of values around the target value; repeating the programming and verifying for each of the N values; and identifying the analog neural non-volatile memory cell as bad if any of the verifying indicates a value stored in the cell outside of the acceptable window of values around the target value.

What is claimed is: 
     
         1 . A method comprising:
 programming an analog neural non-volatile memory cell in an array to a target value representing one of N different values, where N is an integer;   verifying that a value stored in the analog neural non-volatile memory cell is within an acceptable window of values around the target value;   repeating the programming and verifying for each of the N values; and   identifying the analog neural non-volatile memory cell as bad if any of the verifying indicates a value stored in the cell outside of the acceptable window of values around the target value.   
     
     
         2 . The method of  claim 1 , wherein the analog neural non-volatile memory cell is a stacked-gate flash memory cell. 
     
     
         3 . The method of  claim 1 , wherein the analog neural non-volatile memory cell is a split-gate flash memory cell. 
     
     
         4 . The method of  claim 1 , wherein the array is part of a neural network. 
     
     
         5 . A system comprising:
 an array of analog neural non-volatile memory cells; and   test control logic to perform a read window check test comprising:
 programming a selected analog neural non-volatile memory cell in the array to a target value representing one of N different values, where N is an integer; 
 verifying that a value stored in the selected analog neural non-volatile memory cell is within an acceptable window of values around the target value; 
 repeating the programming and verifying for each of the N values; and 
 identifying the selected analog neural non-volatile memory cell as bad if any of the verifying indicates a value stored in the cell outside of the acceptable window of values around the target value. 
   
     
     
         6 . The system of  claim 5 , wherein the selected analog neural non-volatile memory cell is a stacked-gate flash memory cell. 
     
     
         7 . The system of  claim 5 , wherein the selected analog neural non-volatile memory cell is a split-gate flash memory cell. 
     
     
         8 . The system of  claim 5 , wherein the array is part of a neural network.