Memory system and data transmission method

Abstract

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

What is claimed is: 
     
         1 . A memory module comprising:
 a substrate;   a first plurality of memory circuits mounted on a left side of a front surface of said substrate;   a second plurality of memory circuits mounted on a right side of the front surface of said substrate;   first pins for receiving first command and address signals for controlling the first plurality of memory circuits; and   second pins for receiving second command and address signals for controlling the second plurality of memory circuits.   
     
     
         2 . The memory module as claimed in  claim 1 , further comprising:
 a first buffer circuit for receiving the first command and address signals and providing first buffered command and address signals to the first plurality of memory circuits; and   a second buffer circuit for receiving the second command and address signals and providing second buffered command and address signals to the second plurality of memory circuits.   
     
     
         3 . The memory module as claimed in  claim 1 , further comprising:
 a third pin for receiving a first clock signal synchronous with the first command and address signals; and   a fourth pin for receiving a second clock signal synchronous with the second command and address signals.   
     
     
         4 . The memory module as claimed in  claim 1 , further comprising:
 third pins for receiving first data signals for writing the first plurality of memory circuits; and   fourth pins for receiving second data signals for writing the second plurality of memory circuits.   
     
     
         5 . The memory module as claimed in  claim 1 , further comprising:
 a third plurality of memory circuits mounted on a back surface of said substrate opposite the first plurality of memory circuits; and   a fourth plurality of memory circuits mounted on a back surface of said substrate opposite the second plurality of memory circuits;   wherein the first command and address signals control the third plurality of memory circuits; and   wherein the second command and address signals control the fourth plurality of memory circuits.   
     
     
         6 . The memory module as claimed in  claim 1 , wherein the first pins are located on the left side of the substrate and the second pins are located on the right side of the substrate. 
     
     
         7 . The memory module as claimed in  claim 1 , wherein the first plurality of memory circuits is four memory circuits and the second plurality of memory circuits is four memory circuits. 
     
     
         8 . The memory module as claimed in  claim 1 , wherein the first plurality of memory circuits is four memory circuits and the second plurality of memory circuits is five memory circuits. 
     
     
         9 . A memory system comprising:
 a memory controller having:
 first pins for outputting first command and address signals; and 
 second pins for outputting second command and address signals; 
   a memory module having:
 a substrate; 
 a first plurality of memory circuits mounted on a left side of a front surface of said substrate; 
 a second plurality of memory circuits mounted on a right side of the front surface of said substrate; 
 third pins for receiving the first command and address signals for controlling the first plurality of memory circuits; and 
 fourth pins for receiving the second command and address signals for controlling the second plurality of memory circuits; 
   first wiring connecting first pins and third pins; and   second wiring connecting second pins and fourth pins.   
     
     
         10 . The memory system as claimed in  claim 9 , wherein the memory module further comprises:
 a first buffer circuit for receiving the first command and address signals and providing first buffered command and address signals to the first plurality of memory circuits; and   a second buffer circuit for receiving the second command and address signals and providing second buffered command and address signals to the second plurality of memory circuits.   
     
     
         11 . The memory system as claimed in  claim 9 , further comprising:
 a fifth pin on the memory controller for outputting a first clock signal synchronous with the first command and address signals;   a sixth pin on the memory controller for outputting a second clock signal synchronous with the second command and address signals;   a seventh pin on the memory module for receiving the first clock signal;   an eighth pin on the memory module for receiving the second clock signal;   third wiring connecting the fifth pin and the seventh pin; and   fourth wiring connecting the sixth pin and the eighth pin.   
     
     
         12 . The memory system as claimed in  claim 9 , further comprising:
 fifth pins on the memory controller for outputting first data signals;   sixth pins on the memory controller for outputting second data signals;   seventh pins on the memory module for receiving the first data signals;   eighth pins on the memory module for receiving the second data signals;   third wiring connecting the fifth pin and the seventh pin; and   fourth wiring connecting the sixth pin and the eighth pin.   
     
     
         13 . The memory system as claimed in  claim 9 , wherein the memory module further comprises:
 a third plurality of memory circuits mounted on a back surface of said substrate opposite the first plurality of memory circuits; and   a fourth plurality of memory circuits mounted on a back surface of said substrate opposite the second plurality of memory circuits;   wherein the first command and address signals control the third plurality of memory circuits; and   wherein the second command and address signals control the fourth plurality of memory circuits.   
     
     
         14 . The memory system as claimed in  claim 9 , wherein the third pins are located on the left side of the substrate and the fourth pins are located on the right side of the substrate. 
     
     
         15 . The memory system as claimed in  claim 9 , wherein the first plurality of memory circuits is four memory circuits and the second plurality of memory circuits is four memory circuits. 
     
     
         16 . The memory system as claimed in  claim 9 , wherein the first plurality of memory circuits is four memory circuits and the second plurality of memory circuits is five memory circuits. 
     
     
         17 . The memory system as claimed in  claim 9 , wherein the first command and address signals and the second command and address signals are outputted simultaneously. 
     
     
         18 . A method comprising:
 outputting first command and address signals to first pins of a memory controller;   outputting second command and address signals to second pins of the memory controller;   receiving the first command and address signals at third pins of a memory module;   receiving the second command and address signals at fourth pins of the memory module;   controlling a first plurality of memory circuits mounted on a left side of a front surface of the memory module with the first command and address signals; and   controlling a second plurality of memory circuits mounted on a right side of the front surface of the memory module with the second command and address signals.   
     
     
         19 . The method as claimed in  claim 18 , wherein:
 the first command and address signals are inputted to a first buffer circuit on the memory module which provides first buffered command and address signals to the first plurality of memory circuits; and   the second command and address signals are inputted to a second buffer circuit on the memory module which provides second buffered command and address signals to the second plurality of memory circuits.   
     
     
         20 . The method as claimed in  claim 18 , further comprising:
 outputting a first clock signal synchronous with the first command and address signals to a fifth pin of the memory controller;   outputting a second clock signal synchronous with the second command and address signals to a sixth pin of the memory controller;   receiving the first clock signal at a seventh pin of the memory module; and   receiving the second clock signal at an eighth pin of the memory module.   
     
     
         21 . The method as claimed in  claim 18 , further comprising:
 outputting first data signals to fifth pins of the memory controller;   outputting second data signals to sixth pins of the memory controller;   receiving the first data signals at seventh pins on the memory module;   receiving the second data signals at eighth pins on the memory module;   writing the first data signals to the first plurality of memory circuits; and   writing the second data signals to the second plurality of memory circuits.   
     
     
         22 . The method as claimed in  claim 18 , wherein the memory module further comprises:
 controlling a third plurality of memory circuits mounted on a back surface of the memory module with the first command and address signals; and   controlling a fourth plurality of memory circuits mounted on the back surface of the memory module with the second command and address signals.   
     
     
         23 . The method as claimed in  claim 18 , wherein the third pins are located on the left side of the module and the fourth pins are located on the right side of the module. 
     
     
         24 . The method as claimed in  claim 18 , wherein the first plurality of memory circuits is four memory circuits and the second plurality of memory circuits is four memory circuits. 
     
     
         25 . The method as claimed in  claim 18 , wherein the first plurality of memory circuits is four memory circuits and the second plurality of memory circuits is five memory circuits. 
     
     
         26 . The method as claimed in  claim 18 , wherein the first command and address signals and the second command and address signals are outputted simultaneously.