Gate-Controlled Charge Modulated Device for CMOS Image Sensors

Abstract

A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

What is claimed is: 
     
         1 . A device for sensing light, the device comprising:
 a first semiconductor region doped with a dopant of a first type;   a second semiconductor region doped with a dopant of a second type, wherein:
 the second semiconductor region is positioned above the first semiconductor region; and 
 the first type is distinct from the second type; 
   a gate insulation layer positioned above the second semiconductor region;   a gate positioned above the gate insulation layer;   a source electrically coupled with the second semiconductor region; and   a drain electrically coupled with the second semiconductor region, wherein:
 the second semiconductor region has a top surface that is positioned toward the gate insulation layer; 
 the second semiconductor region has a bottom surface that is positioned opposite to the top surface of the second semiconductor region; 
 the second semiconductor region has an upper portion that includes the top surface of the second semiconductor region; 
 the second semiconductor region has a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion; 
 the upper portion of the second semiconductor region extends from the source to the drain; 
 the lower portion of the second semiconductor region extends from the source to the drain; 
 the first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region; and 
 the first semiconductor region is in contact with the upper portion of the second semiconductor region at least at a location positioned under the gate.