System, apparatus and method for fine-grain address space selection in a processor

Abstract

In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

1 . (canceled) 
     
     
         2 . A processor comprising:
 a decoder to decode an enqueue command instruction from software in a virtual machine, the enqueue command instruction having a first field to represent a destination operand and a second field to represent a source memory operand; and   an execution circuit coupled to the decoder, wherein in response to the decoded enqueue command instruction, the processor is to:
 read command data from a memory location identified by the source memory operand; 
 use first process address space identifier (PASID) information from a configuration register to access a PASID translation structure to obtain a second PASID; 
 format the command data to include the second PASID; and 
 write the formatted command data to a location identified by the destination operand. 
   
     
     
         3 . The processor of  claim 2 , wherein the PASID translation structure comprises at least one PASID directory and at least one PASID table. 
     
     
         4 . The processor of  claim 3 , wherein the processor is to access a pointer in a virtual machine control structure to obtain a directory pointer. 
     
     
         5 . The processor of  claim 4 , wherein the processor is to access the at least one PASID directory using the directory pointer. 
     
     
         6 . The processor of  claim 3 , wherein the processor is to obtain a PASID table pointer from the at least one PASID directory. 
     
     
         7 . The processor of  claim 6 , wherein the processor is to use the PASID table pointer to access an entry in the at least one PASID table. 
     
     
         8 . The processor of  claim 7 , wherein the processor is to obtain the second PASID from the at least one PASID table. 
     
     
         9 . The processor of  claim 2 , wherein the processor is to replace a portion of the command data with the second PASID. 
     
     
         10 . The processor of  claim 2 , wherein the processor is to write the formatted command data to the location in a device, the location comprising an enqueue register of the device. 
     
     
         11 . The processor of  claim 2 , wherein the processor is to write the formatted command data to a device comprising an accelerator. 
     
     
         12 . The processor of  claim 2 , wherein the processor is to receive the first PASID information comprising guest PASID information and wherein the second PASID comprises a host PASID. 
     
     
         13 . A method comprising:
 decoding, in a processor, an enqueue command instruction from software in a virtual machine, the enqueue command instruction having a first field representing a destination operand and a second field representing a source memory operand;   reading, by the processor, command data from a memory location identified by the source memory operand, the command data comprising guest information of the virtual machine;   obtaining first process address space identifier (PASID) information from a configuration register;   using the first PASID information to access a PASID translation structure to obtain a second PASID;   formatting the command data to include the second PASID, the command data comprising host information of a host; and   writing the formatted command data to a location in a device coupled to the processor, the location identified by the destination operand.   
     
     
         14 . The method of  claim 13 , further comprising:
 accessing a pointer in a virtual machine control structure to obtain a directory pointer; and   accessing a PASID directory of the PASID translation structure using the directory pointer to obtain a PASID table pointer.   
     
     
         15 . The method of  claim 14 , further comprising using the PASID table pointer to access an entry in a PASID table of the PASID translation structure, to obtain the second PASID. 
     
     
         16 . The method of  claim 13 , further comprising writing the formatted command data to the location comprising an enqueue register in the device. 
     
     
         17 . A system comprising:
 a processor comprising:
 a configuration register; 
 a decoder to decode an enqueue command instruction from software in a virtual machine, the enqueue command instruction having a first field to represent a destination operand and a second field to represent a source memory operand; and 
 an execution circuit coupled to the decoder, wherein in response to the decoded enqueue command instruction, the processor is to:
 read command data from a memory location identified by the source memory operand; 
 obtain first process address space identifier (PASID) information from the configuration register; 
 use the first PASID information to access a PASID translation structure to obtain a second PASID; 
 format the command data to include the second PASID; and 
 write the formatted command data to a location identified by the destination operand, to cause the formatted command data to be stored in a device coupled to the processor; and 
 
   the device coupled to the processor, the device comprising an enqueue register, wherein the device is to store the formatted command data in the enqueue register.   
     
     
         18 . The system of  claim 17 , wherein the device comprises an accelerator. 
     
     
         19 . The system of  claim 18 , wherein the accelerator comprises a data streaming accelerator. 
     
     
         20 . The system of  claim 17 , wherein the device comprises a scalable input/output (I/O) virtualization device. 
     
     
         21 . The system of  claim 17 , wherein the enqueue register is to be accessed using memory mapped input output (MMIO).