Source/drain contacts for non-planar transistors

Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

What is claimed is: 
     
         1 . A method of fabricating a microelectronic device, comprising:
 forming a silicon-containing non-planar fin;   forming a source or drain region on the silicon-containing non-planar fin;   forming a dielectric material over the source or drain region;   forming a contact opening through the dielectric material to expose a portion of the source or drain region;   forming an interface within the contact opening and on the source or drain region, wherein the interface comprises titanium and silicon;   forming a titanium-containing contact interface layer within the contact opening and on the interface; and   forming a conductive contact material within the contact opening and on the titanium-containing contact interface layer.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a gate electrode over the silicon-containing non-planar fin, the gate electrode laterally spaced apart from the contact opening.   
     
     
         3 . The method of  claim 1 , further comprising:
 forming a capping structure on the gate electrode.   
     
     
         4 . The method of  claim 3 , wherein a portion of the titanium-containing contact interface layer is on the capping structure. 
     
     
         5 . The method of  claim 3 , wherein a portion of the titanium-containing contact interface layer is in direct contact with the capping structure. 
     
     
         6 . The method of  claim 1 , further comprising:
 forming a gate spacer along a side of the gate electrode, the gate spacer laterally between the gate electrode and the contact opening.   
     
     
         7 . The method of  claim 1 , further comprising:
 forming a capping structure on the gate electrode; and   forming a gate spacer along a side of the gate electrode and along a side of the capping structure, the gate spacer laterally between the gate electrode and the contact opening, and the gate spacer having an uppermost surface co-planar with an uppermost surface of the capping structure.   
     
     
         8 . The method of  claim 7 , wherein a portion of the gate spacer is in direct contact with the capping structure. 
     
     
         9 . The method of  claim 7 , further comprising:
 forming a second dielectric material on the dielectric material, on the uppermost surface of the capping structure and on the uppermost surface of the gate spacer, the second dielectric material having an uppermost surface co-planar with an uppermost surface of the conductive contact material.   
     
     
         10 . A microelectronic device, comprising:
 a silicon-containing body;   a source or drain region on the silicon-containing body;   a dielectric material over the source or drain region;   a contact opening through the dielectric material to expose a portion of the source or drain region;   an interface within the contact opening and on the source or drain region, wherein the interface comprises titanium and silicon;   a titanium-containing contact interface layer within the contact opening and on the interface; and   a conductive contact material within the contact opening and on the titanium-containing contact interface layer.   
     
     
         11 . The microelectronic device of  claim 10 , wherein the silicon-containing body is a fin. 
     
     
         12 . The microelectronic device of  claim 10 , further comprising:
 a gate electrode over the silicon-containing body, the gate electrode laterally spaced apart from the contact opening.   
     
     
         13 . The microelectronic device of  claim 10 , further comprising:
 a capping structure on the gate electrode.   
     
     
         14 . The microelectronic device of  claim 13 , wherein a portion of the titanium-containing contact interface layer is on the capping structure. 
     
     
         15 . The microelectronic device of  claim 10 , further comprising:
 a capping structure on the gate electrode; and   a gate spacer along a side of the gate electrode and along a side of the capping structure, the gate spacer laterally between the gate electrode and the contact opening, and the gate spacer having an uppermost surface co-planar with an uppermost surface of the capping structure.   
     
     
         16 . The microelectronic device of  claim 15 , further comprising:
 a second dielectric material on the dielectric material, on the uppermost surface of the capping structure and on the uppermost surface of the gate spacer, the second dielectric material having an uppermost surface co-planar with an uppermost surface of the conductive contact material.   
     
     
         17 . A method of fabricating a microelectronic device, comprising:
 forming a non-planar semiconductor body;   forming a source or drain region on the non-planar semiconductor body;   forming a dielectric material over the source or drain region;   forming a contact opening through the dielectric material to expose a portion of the source or drain region;   forming an interface within the contact opening and on the source or drain region, wherein the interface comprises titanium and silicon;   forming a titanium-containing contact interface layer within the contact opening and on the interface; and   forming a conductive contact material within the contact opening and on the titanium-containing contact interface layer.   
     
     
         18 . The method of  claim 17 , further comprising:
 forming a gate electrode over the non-planar semiconductor body, the gate electrode laterally spaced apart from the contact opening.   
     
     
         19 . The method of  claim 17 , further comprising:
 forming a capping structure on the gate electrode.   
     
     
         20 . The method of  claim 19 , wherein a portion of the titanium-containing contact interface layer is on the capping structure. 
     
     
         21 . The method of  claim 17 , further comprising:
 forming a capping structure on the gate electrode; and   forming a gate spacer along a side of the gate electrode and along a side of the capping structure, the gate spacer laterally between the gate electrode and the contact opening, and the gate spacer having an uppermost surface co-planar with an uppermost surface of the capping structure.   
     
     
         22 . The method of claim  121 , further comprising:
 forming a second dielectric material on the dielectric material, on the uppermost surface of the capping structure and on the uppermost surface of the gate spacer, the second dielectric material having an uppermost surface co-planar with an uppermost surface of the conductive contact material.