Code update in system management mode

Abstract

A computing device is provided, including memory storing an instruction storage location. The computing device may further include a processor system including a plurality of processor threads. The processor system may suspend execution of one or more respective processor threads of the plurality of processor threads. The processor system may store one or more respective processor thread contexts of the one or more processor threads in the memory. The processor system may enter a system management mode (SMM). The processor system may determine that the instruction storage location includes a code update instruction. The processor system may perform a code update based on the code update instruction. The processor system may exit the SMM. The processor system may retrieve the one or more processor thread contexts from the memory and resume execution of the one or more processor threads without rebooting the computing device.

1 . A computing device comprising:
 memory including a system management memory region; and   a processor system including a plurality of processor threads, wherein the processor system is configured to:
 suspend execution of one or more processor threads of the plurality of processor threads; 
 store one or more respective processor thread contexts of the one or more processor threads in the memory; 
 enter a system management mode (SMM); 
 determine that the system management memory region includes a code update instruction at least in part by querying a lookup table indicating a respective location in the memory of each of a plurality of system management interrupt (SMI) handlers included in an SMI handler list, wherein:
 the SMI handler list includes an update query SMI handler; and 
 querying the lookup table includes executing the update query SMI handler; 
 
 perform a code update based on the code update instruction, wherein performing the code update includes:
 modifying the SMI handler list; and 
 executing the plurality of SMI handlers in the modified SMI handler list; 
 
 exit the SMM; 
 retrieve the one or more processor thread contexts from the memory; and 
 resume execution of the one or more processor threads without rebooting the computing device. 
   
     
     
         2 . The computing device of  claim 1 , wherein:
 the code update instruction includes an instruction to modify the SMI handler list at least in part by adding an additional SMI handler to the SMI handler list or removing an SMI handler included among the plurality of SMI handlers from the SMI handler list; and   the modified SMI handler list includes a handler override indicating the modification.   
     
     
         3 . The computing device of  claim 1 , wherein the code update instruction includes an instruction to reinitialize at least a part of a memory controller of the memory. 
     
     
         4 . The computing device of  claim 1 , wherein the code update instruction includes an instruction to:
 change a multithreading setting of the processor system; or   enable or disable a core of the processor system.   
     
     
         5 . The computing device of  claim 1 , wherein:
 the code update instruction includes an instruction to modify a memory usage model of the memory; and   the modification to the memory usage model includes a modification to a size and/or a location of a mirrored address range in the memory.   
     
     
         6 . The computing device of  claim 1 , wherein the processor system is further configured to execute one or more virtual machines concurrently with the SMM. 
     
     
         7 . The computing device of  claim 1 , wherein, during execution of the update query SMI handler, the processor system retrieves the code update instruction from the lookup table. 
     
     
         8 . The computing device of  claim 1 , wherein the processor system is further configured to:
 designate a processor thread selected from among the plurality of processor threads as a monarch thread; and   execute the plurality of SMI handlers at the monarch thread.   
     
     
         9 . The computing device of  claim 8 , wherein, by executing the monarch thread, the processor system is further configured to assign the plurality of SMI handlers to respective processor threads of the plurality of processor threads. 
     
     
         10 . The computing device of  claim 1 , wherein the execution of the one or more processor threads is resumed without receiving the one or more processor thread contexts from an additional computing device. 
     
     
         11 . A method for use with a computing device, the method comprising:
 suspending execution of one or more processor threads of a plurality of processor threads executed by a processor system;   storing one or more respective processor thread contexts of the one or more processor threads in memory;   entering a system management mode (SMM);   determining that a system management memory region of the memory includes a code update instruction at least in part by querying a lookup table indicating a respective location in the memory of each of a plurality of system management interrupt (SMI) handlers included in an SMI handler list, wherein:
 the SMI handler list includes an update query SMI handler; and 
 querying the lookup table includes executing the update query SMI handler; 
   performing a code update based on the code update instruction, wherein performing the code update includes:
 modifying the SMI handler list; and 
 executing the plurality of SMI handlers in the modified SMI handler list; 
   exiting the SMM;   retrieving the one or more processor thread contexts from the memory; and   resuming execution of the one or more processor threads without rebooting the computing device.   
     
     
         12 . The method of  claim 11 , wherein:
 the code update instruction includes an instruction to modify the SMI handler list at least in part by adding an additional SMI handler to the SMI handler list or removing an SMI handler included among the plurality of SMI handlers from the SMI handler list; and   the modified SMI handler list includes a handler override indicating the modification.   
     
     
         13 . The method of  claim 11 , wherein the code update instruction includes an instruction to reinitialize at least a part of a memory controller of the memory. 
     
     
         14 . The method of  claim 11 , wherein the code update instruction includes an instruction to:
 change a multithreading setting of the processor system; or   enable or disable a core of the processor system.   
     
     
         15 . The method of  claim 11 , further comprising executing one or more virtual machines concurrently with the SMM. 
     
     
         16 . The method of  claim 11 , further comprising, during execution of the update query SMI handler, retrieving the code update instruction from the lookup table. 
     
     
         17 . The method of  claim 11 , further comprising:
 designating a processor thread selected from among the plurality of processor threads as a monarch thread; and   executing the plurality of SMI handlers at the monarch thread.   
     
     
         18 . The method of  claim 17 , further comprising, by executing the monarch thread, assigning the plurality of SMI handlers to respective processor threads of the plurality of processor threads. 
     
     
         19 . The method of  claim 11 , wherein the execution of the one or more processor threads is resumed without receiving the one or more processor thread contexts from an additional computing device. 
     
     
         20 . A computing device comprising:
 memory including a system management memory region; and   a processor system including a plurality of processor threads, wherein the processor system is configured to:
 suspend execution of one or more processor threads of the plurality of processor threads; 
 store one or more respective processor thread contexts of the one or more processor threads in the memory; 
 designate a processor thread selected from among the plurality of processor threads as a monarch thread; 
 enter a system management mode (SMM); 
 determine that the system management memory region includes a code update instruction at least in part by querying a lookup table indicating a respective location in the memory of each of a plurality of system management interrupt (SMI) handlers included in an SMI handler list, wherein:
 the SMI handler list includes an update query SMI handler; 
 querying the lookup table includes executing the update query SMI handler; and 
 executing the update query SMI handler includes retrieving the code update instruction from the lookup table; 
 
 perform a code update based on the code update instruction, wherein performing the code update includes:
 modifying the SMI handler list; and 
 executing the plurality of SMI handlers in the modified SMI handler list at the monarch thread; 
 
 exit the SMM; 
 retrieve the one or more processor thread contexts from the memory; and 
 resume execution of the one or more processor threads without rebooting the computing device.