Compact CMOS in wide bandgap semiconductor

Abstract

CMOS Systems formed in Wide Bandgap Semiconductor and involving use of a material that forms a rectifying junction with either N and P-type Field Induced Semiconductor, in combination with, preferably, Parallel and Adjacent Channels subject to control by a Gate removed from said Channels by insulator.

We claim: 
     
         1 . A CMOS structure comprising a region of material in a wide bandgap substrate which forms rectifying junctions with both field induced N and P-type regions therein,
 said CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a said wide bandgap substrate which forms rectifying junctions with both field induced N and P-type regions therein;   said CMOS structure further comprising gate structures offset with respect to said channels by insulating material;   said CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type wide bandgap semiconductor, at distal ends of said at least two channels;   said wide bandgap semiconductor substrate, at least in the regions of said channels being characterized by a selection from the group consisting of:
 it is substantially or per se. intrinsic; 
 it is substantially or per se. metallurigically compensated; 
 it contains both metallurgical N and P-type dopants in unequal concentrations; 
 it is metallurgically doped to provide at least one area of P-type material and at least one separate area of N-type material in each channel region; 
   such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type wide bandgap semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type silicon carbide is low, and vice-versa.   
     
     
         2 . A CMOS structure as in  claim 1 , in which the wide bandgap semiconductor is selected from the group consisting of:
 silicon carbide (SiC);   gallium nitride (GaN)   gallium arsenide (GaAs);   zinc oxide (ZnO); and   diamond (C).   
     
     
         3 . A CMOS structure comprising a region of material in a silicon carbide substrate which forms rectifying junctions with both field induced N and P-type silicon carbide,
 said CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a silicon carbide substrate which forms rectifying junctions with both field induced N and P-type silicon carbide;   said CMOS structure further comprising gate structures offset with respect to said channels by insulating material;   said CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type silicon carbide, and to distal ends of said at least two channels;   said silicon carbide substrate, at least in the regions of said channels being characterized by a selection from the group consisting of:
 it is substantially or per se. intrinsic; 
 it is substantially or per se. metallurigically compensated; 
 it contains both metallurgical N and P-type dopants in unequal concentrations; 
 it is metallurgically doped to provide at least one area of P-type material and at least one separate area of N-type material in each channel region; 
   such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type silicon carbide which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type silicon carbide is low, and vice-versa.   
     
     
         4 . A CMOS structure as in  claim 3 , in which the material in said silicon carbide substrate which forms rectifying junctions with both field induced N and P-type silicon carbide, is vanadium doped silicon carbide. 
     
     
         5 . A CMOS structure as in  claim 3 , in which the material comprising substantially non-rectifying junctions to said distal regions of channels comprises nickel. 
     
     
         6 . A compact CMOS structure comprising a region of material in a silicon carbide substrate which forms rectifying junctions with both field induced N and P-type silicon carbide,
 said compact CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a silicon carbode substrate which forms rectifying junctions with both field induced N and P-type silicon carbide, said channels being substantially parallel and adjacent to one another;   said compact CMOS structure further comprising a gate structure offset with respect to said channels by insulating material;   said compact CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type silicon carbide, and to distal ends of said at least two channels;   said silicon carbide substrate, at least in the regions of said channels being characterized by a selection from the group consisting of:
 it is substantially or per se. intrinsic; 
 it is substantially or per se. metallurigically compensated; 
 it contains both metallurgical N and P-type dopants in unequal concentrations; 
 it is metallurgically doped to provide at least one area of P-type material and at least one separate area of N-type material in each channel region; 
   such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type silicon carbide which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type silicon carbide is low, and vice-versa.   
     
     
         7 . A compact CMOS structure as in  claim 6 , in which the material in said silicon carbide substrate which forms rectifying junctions with both field induced N and P-type silicon carbide, is vanadium doped silicon carbide. 
     
     
         8 . A compact CMOS structure as in  claim 6 , in which the material comprising substantially non-rectifying junctions to said distal regions of channels comprises nickel. 
     
     
         9 . A CMOS structure as in  claim 1 , in which said channels are present in FINS which project from a surface of said wide bandgap semiconductor substrate. 
     
     
         10 . A CMOS structure as in  claim 3 , in which said channels are present in FINS which project from a surface of said wide bandgap semiconductor substrate. 
     
     
         11 . A compact CMOS structure as in  claim 6 , in which said channels are present in FINS which project from a surface of said wide bandgap semiconductor substrate.