Assessing risk of future uncorrectable memory errors with fully correctable patterns of error correction code

Abstract

Systems, apparatuses and methods may provide for technology that identifies a plurality of fully correctable patterns associated with an error correction code (ECC) in a memory controller, detects one or more correctable errors in a memory module coupled to the memory controller, and generates an alert if an error-bit pattern of the one or more correctable errors does not match one or more of the plurality of fully correctable patterns.

We claim: 
     
         1 . A memory controller comprising:
 one or more substrates; and   logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:   identify a plurality of fully correctable patterns associated with an error correction code (ECC) in the memory controller;   detect one or more correctable errors in a memory module coupled to the memory controller; and   generate an alert if an error-bit pattern of the one or more correctable errors does not match any of the plurality of fully correctable patterns.   
     
     
         2 . The memory controller of  claim 1 , wherein one or more bits of the ECC are reallocated to non-error detection operations. 
     
     
         3 . The memory controller of  claim 1 , wherein the error-bit pattern is a cumulative error-bit pattern. 
     
     
         4 . The memory controller of  claim 1 , wherein the alert predicts a future uncorrectable error. 
     
     
         5 . The memory controller of  claim 1 , wherein the alert is generated further based on micro-level fault data. 
     
     
         6 . The memory controller of  claim 1 , wherein the alert is generated further based on a part number associated with the memory module. 
     
     
         7 . The memory controller of  claim 1 , wherein generation of the alert includes one or more of an activation of a telemetry indicator, a storage of the alert to a serial presence detect (SPD) table in the memory module, or a storage of the alert to a system non-volatile memory. 
     
     
         8 . A computing system comprising:
 a memory module; and   a memory controller coupled to the memory module, wherein the memory controller includes logic coupled to one or more substrates, the logic to:
 identify a plurality of fully correctable patterns associated with an error correction code (ECC) in the memory controller, 
 detect one or more correctable errors in the memory module, and 
 generate an alert if an error-bit pattern of the one or more correctable errors does not match any of the plurality of fully correctable patterns. 
   
     
     
         9 . The computing system of  claim 8 , wherein one or more bits of the ECC are reallocated to non-error detection operations. 
     
     
         10 . The computing system of  claim 8 , wherein the error-bit pattern is a cumulative error-bit pattern. 
     
     
         11 . The computing system of  claim 8 , wherein the alert predicts a future uncorrectable error. 
     
     
         12 . The computing system of  claim 8 , wherein the alert is generated further based on one or more of micro-level fault data or a part number associated with the memory module. 
     
     
         13 . The computing system of  claim 8 , wherein generation of the alert includes one or more of an activation of a telemetry indicator, a storage of the alert to a serial presence detect (SPD) table in the memory module, or a storage of the alert to a system non-volatile memory. 
     
     
         14 . At least one computer readable storage medium comprising a set of executable program instructions, which when executed by a memory controller, cause the memory controller to:
 identify a plurality of fully correctable patterns associated with an error correction code (ECC) in the memory controller;   detect one or more correctable errors in a memory module coupled to the memory controller; and   generate an alert if an error-bit pattern of the one or more correctable errors does not match one or more of the plurality of fully correctable patterns.   
     
     
         15 . The at least one computer readable storage medium of  claim 14 , wherein one or more bits of the ECC are reallocated to non-error detection operations. 
     
     
         16 . The at least one computer readable storage medium of  claim 14 , wherein the error-bit pattern is a cumulative error-bit pattern. 
     
     
         17 . The at least one computer readable storage medium of  claim 14 , wherein the alert predicts a future uncorrectable error. 
     
     
         18 . The at least one computer readable storage medium of  claim 14 , wherein the alert is generated further based on micro-level fault data. 
     
     
         19 . The at least one computer readable storage medium of  claim 14 , wherein the alert is generated further based on a part number associated with the memory module. 
     
     
         20 . The at least one computer readable storage medium of  claim 14 , wherein generation of the alert includes one or more of an activation of a telemetry indicator, a storage of the alert to a serial presence detect (SPD) table in the memory module, or a storage of the alert to a system non-volatile memory.