Scalable runtime validation for on-device design rule checks

Abstract

An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, multiplexers, and a validator. In one implementation, the validator is to: receive design rule information for the multiplexers, the design rule information referencing the contention set, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the multiplexers; receive, at the validator of the apparatus, the user bitstream for programming the multiplexers of the apparatus; analyze, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the apparatus; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

What is claimed is: 
     
         1 . An apparatus comprising:
 a memory to store a contention set;   one or more multiplexers; and   a validator communicably coupled to the memory, the validator to:
 receive design rule information for the one or more multiplexers, the design rule information referencing the contention set, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the one or more multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the one or more multiplexers; 
 receive, at the validator of the apparatus, the user bitstream for programming the one or more multiplexers of the apparatus; 
 analyze, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the apparatus; and 
 provide an error indication responsive to identifying a match between the user bitstream and the contention set. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the contention set comprises information identifying where routing intellectual properties (IPs) are located on each row of the apparatus, identifying frames and frames bits configured for each of the one or more multiplexers in the routing IPs, and configuration rules. 
     
     
         3 . The apparatus of  claim 1 , wherein the contention set is generated by an electronic design automation (EDA) tool. 
     
     
         4 . The apparatus of  claim 1 , wherein validator is to process configuration frames of the contention set at least one of one by one or in chunks. 
     
     
         5 . The apparatus of  claim 1 , wherein the one or more multiplexers comprise one or more routing multiplexers. 
     
     
         6 . The apparatus of  claim 1 , wherein the apparatus comprises a hardware accelerator device comprising at least one a graphic processing unit (GPU), a central processing unit (CPU), or a programmable integrated circuit (IC). 
     
     
         7 . The apparatus of  claim 6 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD). 
     
     
         8 . A method comprising:
 receiving, by a validator of a hardware accelerator device, design rule information for the one or more multiplexers, the design rule information referencing the contention set, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the one or more multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the one or more multiplexers;   receiving, at the validator of the hardware accelerator device, the user bitstream for programming the one or more multiplexers of the apparatus;   analyzing, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the hardware accelerator device; and   providing, by the validator, an error indication responsive to identifying a match between the user bitstream and the contention set.   
     
     
         9 . The method of  claim 8 , wherein the contention set comprises information identifying where routing intellectual properties (IPs) are located on each row of the apparatus, identifying frames and frames bits configured for each of the one or more multiplexers in the routing IPs, and configuration rules. 
     
     
         10 . The method of  claim 8 , wherein the contention set is generated by an electronic design automation (EDA) tool. 
     
     
         11 . The method of  claim 8 , wherein validator is to process configuration frames of the contention set at least one of one by one or in chunks. 
     
     
         12 . The method of  claim 8 , wherein the one or more multiplexers comprise one or more routing multiplexers. 
     
     
         13 . The method of  claim 8 , wherein the hardware accelerator device comprising at least one a graphic processing unit (GPU), a central processing unit (CPU), or a programmable integrated circuit (IC). 
     
     
         14 . The method of  claim 13 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD). 
     
     
         15 . A non-transitory machine readable storage medium comprising instructions that, when executed, cause at least one processor to at least:
 receive, by a validator of a hardware accelerator device comprising the at least one processor, design rule information for the one or more multiplexers, the design rule information referencing the contention set, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the one or more multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the one or more multiplexers;   receive, at the validator of the hardware accelerator device, the user bitstream for programming the one or more multiplexers of the apparatus;   analyze, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the hardware accelerator device; and   provide, by the validator, an error indication responsive to identifying a match between the user bitstream and the contention set.   
     
     
         16 . The non-transitory machine readable storage medium of  claim 15 , wherein the contention set comprises information identifying where routing intellectual properties (IPs) are located on each row of the apparatus, identifying frames and frames bits configured for each of the one or more multiplexers in the routing IPs, and configuration rules. 
     
     
         17 . The non-transitory machine readable storage medium of  claim 15 , wherein the contention set is generated by an electronic design automation (EDA) tool. 
     
     
         18 . The non-transitory machine readable storage medium of  claim 15 , wherein validator is to process configuration frames of the contention set at least one of one by one or in chunks. 
     
     
         19 . The non-transitory machine readable storage medium of  claim 15 , wherein the one or more multiplexers comprise one or more routing multiplexers. 
     
     
         20 . The non-transitory machine readable storage medium of  claim 15 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD).