Methods for Three-Dimensional CMOS Integrated Circuit Formation

Abstract

Disclosed are novel structures and methods for 3D CMOS integrated circuits built with vertical transistors. A gate extension is selectively patterned by first patterning a sacrificial dielectric disposed on a gate material. A 3D CMOS IC comprises vertical transistors of one type constructed in one level and those of an opposite type in another level. The gate of lower-level vertical transistors may be coupled to a top interconnect directly through a 3D gate contact or indirectly through an upper-level via and a lower-level contact. A common-gate coupling may be formed between vertical transistors in different levels through a strapping contact or a gate via. A common-drain coupling may be formed between vertical transistors in different levels by forming upper-level vertical transistor on a piece of conductive film disposed over lower-level vertical transistor with or without an intervening top contact for lower-level vertical transistor.

I/We claim: 
     
         1 . A method of constructing a vertical transistor, comprising:
 providing a substrate;   disposing a conductive film over said substrate;   patterning a semiconductor pillar on said conductive film;   disposing a dielectric film up to a bottom portion of said semiconductor pillar;   disposing a gate dielectric on said semiconductor pillar;   disposing a gate material on said gate dielectric;   disposing and planarizing a sacrificial dielectric on said gate material;   patterning a mask on said sacrificial dielectric;   performing a first dielectric etch with said mask;   removing said mask;   performing a second dielectric etch until said sacrificial dielectric is completely removed outside a region originally covered by said mask;   etching said gate material into a gate and a gate extension;   and wherein:
 said gate surrounds a middle portion of said semiconductor pillar; 
 said gate extension is contiguous with said gate at a bottom side of said gate; 
 said sacrificial dielectric fully covers said gate material after being planarized; 
 said sacrificial dielectric is partly removed during said second dielectric etch within said region originally covered by said mask; and 
 said region comprises said vertical transistor and said gate extension. 
   
     
     
         2 . The method of  claim 1 , wherein:
 said sacrificial dielectric is partly removed during said first dielectric etch.   
     
     
         3 . A method of constructing a 3D CMOS IC, comprising:
 providing a substrate;   constructing a first level on said substrate;   constructing a second level over said first level;   disposing a top interconnect on said second level;   and wherein:
 a method of constructing each of said first level and said second level comprises:
 disposing a conductive film as a first layer; 
 forming a semiconductor pillar on said conductive film; 
 disposing a dielectric film on said conductive film up to a bottom portion of said semiconductor pillar; 
 disposing a gate dielectric on said semiconductor pillar; 
 disposing a gate material on said gate dielectric; 
 patterning a mask over said gate material; 
 etching said gate material into a gate and a gate extension; 
 and wherein:
 said gate surrounds a middle portion of said semiconductor pillar; and 
 said gate extension is contiguous with said gate at a bottom side of said gate. 
 
 
   
     
     
         4 . The method of  claim 3 , further comprising:
 doping said semiconductor pillar of said first level in order to form a vertical transistor of a first type;   doping said semiconductor pillar of said second level in order to form a vertical transistor of a second type;   and wherein:
 said first type and said second type are opposite types. 
   
     
     
         5 . The method of  claim 3 , further comprising:
 obtaining a donor wafer;   doping a first depth of said donor wafer with a first type;   doping a second depth of said donor wafer with a second type immediately below said first depth;   doping a third depth of said donor wafer with said first type immediately below said second depth;   bonding said donor wafer to said substrate on said conductive film of said first level;   cleaving off said donor wafer such that said first region, said second region, and said third region of said donor wafer remain on said conductive film of said first level;   doping a fourth depth of said donor wafer with said second type;   doping a fifth depth of said donor wafer with said first type immediately below said fourth depth;   doping a sixth depth of said donor wafer with said second type immediately below said fifth depth;   bonding said donor wafer to said substrate on said conductive film of said second level; and   cleaving off said donor wafer such that said fourth region, said fifth region, and said sixth region of said donor wafer remain on said conductive film of said second level.   
     
     
         6 . The method of  claim 3 , wherein:
 said conductive film of said second level comprises a first piece;   said first piece of said conductive film of said second level is patterned over and coupled to said semiconductor pillar of said first level; and   said semiconductor pillar of said second level is formed on said first piece of said conductive film of said second level.   
     
     
         7 . The method of  claim 6 , further comprising:
 forming a via in said first level;   forming a via in said second level;   and wherein:
 said conductive film of said second level further comprises a second piece; 
 said conductive film of said first level comprises a first piece; 
 said top interconnect comprises a first piece patterned on said via of said second level; 
 said first piece of said top interconnect extended over and coupled to said semiconductor pillar of said second level; 
 said via of said second level is patterned on said second piece of said conductive film of said second level; 
 said second piece of said conductive film of said second level is patterned on said via of said first level; 
 said via of said first level is patterned on said first piece of said conductive film of said first level; and 
 said semiconductor pillar of said first level is patterned on said first piece of said conductive film of said first level. 
   
     
     
         8 . The method of  claim 6 , further comprising:
 forming a 3D via through said first level and said second level; wherein:
 said conductive film of said first level comprises a first piece; 
 said top interconnect comprises a first piece patterned on said 3D via; 
 said first piece of said top interconnect is extended over and coupled to said semiconductor pillar of said second level; 
 said 3D via is patterned on said first piece of said conductive film of said first level; and 
 said semiconductor pillar of said first level is patterned on said first piece of said conductive film of said first level. 
   
     
     
         9 . The method of  claim 3 , wherein:
 said conductive film of said second level comprises a first piece and a second piece;   said first piece of said conductive film of said second level is patterned over and coupled to said semiconductor pillar of said first level; and   said semiconductor pillar of said second level is formed on said second piece of said conductive film of said second level.   
     
     
         10 . The method of  claim 9 , further comprising:
 forming a via in said first level;   forming a via in said second level;   and wherein:
 said top interconnect comprises a first piece patterned on said via of said second level; 
 said conductive film of said first level comprises a first piece; 
 said first piece of said top interconnect is extended over and coupled to said semiconductor pillar of said second level; 
 said via of said second level is formed on said first piece of said conductive film of said second level; 
 said second piece of said conductive film of said second level is patterned on said via of said first level; 
 said via of said first level is patterned on said first piece of said conductive film of said first level; and 
 said semiconductor pillar of said first level is patterned on said first piece of said conductive film of said first level. 
   
     
     
         11 . The method of  claim 10 , further comprising:
 forming a via in said second level; wherein:
 said conductive film of said second level further comprises a third piece; 
 said via is formed on said third piece of said conductive film of said second level; 
 said first gate contact is formed between said third piece of said conductive film of said second level and said gate extension of said first level; and 
 said first piece of said top interconnect is coupled to said third piece of said conductive film of said second level through said via. 
   
     
     
         12 . The method of  claim 3 , wherein:
 said top interconnect comprises a first piece and a second piece;   said first piece of said top interconnect is coupled to said gate of said second level and said gate of said first level; and   said second piece of said top interconnect is coupled to said conductive film of said second level.   
     
     
         13 . The method of  claim 12 , further comprising:
 forming a first gate contact on said gate extension of said first level;   forming a second gate contact on said gate extension of said second level;   and wherein:
 said first piece of said top interconnect is coupled to said first gate contact; and 
 said second piece of said top interconnect is disposed on said second gate contact. 
   
     
     
         14 . The method of  claim 13 , wherein:
 said first gate contact is formed as a 3D gate contact and extends fully between said first piece of said top interconnect and said gate extension of said first level.   
     
     
         15 . The method of  claim 12 , further comprising:
 forming a first gate contact on said gate extension of said first level;   forming a second gate contact in said second level;   and wherein:
 said conductive film of said second level comprises a first piece; 
 said first piece of said conductive film of said second level is formed on said first gate contact; 
 said first piece of said top interconnect is patterned on said second gate contact; and 
 said second gate contact is formed as a strapping contact for said gate extension of said second level and for said first piece of said conductive film of said second level. 
   
     
     
         16 . The method of  claim 12 , further comprising:
 forming a 3D gate contact on said gate extension of said first level; wherein:
 said first piece of said top interconnect is formed on said 3D gate contact; and 
 said 3D gate contact is formed as a strapping contact for said gate extension of said second level and for said gate extension of said first level. 
   
     
     
         17 . The method of  claim 12 , further comprising:
 forming a gate via on said gate extension of said first level;   forming a gate contact on said gate extension of said second level;   and wherein:
 said first piece of said top interconnect is patterned on said gate contact; and 
 said gate extension of said second level is patterned on said gate via. 
   
     
     
         18 . The method of  claim 12 , further comprising:
 forming a 3D gate contact on said gate extension of said first level; wherein:
 said first piece of said top interconnect is patterned on said 3D gate contact; and 
 a process used in forming said 3D gate contact etches through said gate extension of said second level in order to reach said gate extension of said first level.