Semiconductor Package

Abstract

An electronic device includes a graphic processor and a memory device. The graphic processor includes an artificial neural network engine that makes an object recognition model learn by using learning data and weights to provide a learned object recognition model. The memory device, divides a feature vector into a first sub feature vector and a second feature vector, and performs a first calculation to apply the second sub feature vector and the weights to the learned object recognition model to provide a second object recognition result. The artificial neural network engine performs a second calculation to apply the first sub feature vector and the weights to the learned object recognition model to provide a first object recognition result and provides the first object recognition result to the memory device. The second calculation is performed in parallel with the first calculation.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a data processor mounted on an interposer, the data processor including neural network engine; and   one or more stacked memory devices mounted on the interposer, at least one stacked memory device of the one or more stacked memory devices including buffer die which includes a processor in memory (PIM) circuit   wherein the neural network engine is to perform a first calculation to apply a first portion of input data and the PIM circuit is configured to perform a second calculation to apply a second portion of the input data.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the at least one stacked memory device is configured to receive the input data, to store the input data, to divide the input data into the first portion for the neural network engine and the second portion for the PIM circuit and to provide each portion of the input data to the neural network engine and the PIM circuit. 
     
     
         3 . The semiconductor package of  claim 1 , wherein the at least one stacked memory device is configured to provide learning data and weights to the data processor. 
     
     
         4 . The semiconductor package of  claim 1 , wherein the data processor is configured to make an object recognition model learned by using received learning data and weights and to provide a learned object recognition model to the at least one stacked memory device. 
     
     
         5 . The data processor of  claim 4 , wherein the neural network engine in the data processor is configured to generate the object recognition model. 
     
     
         6 . The semiconductor package of  claim 1 , wherein the at least one stacked memory device and the neural network engine are configured to perform calculation to apply each portion of the input data and the weights to the learned object recognition model. 
     
     
         7 . The semiconductor package of  claim 1 , wherein the PIM circuit and the neural network engine are configured to calculate feature vector extracted from the input data received from the at least one stacked memory device. 
     
     
         8 . The semiconductor package of  claim 1 , wherein the neural network engine is configured to provide calculated result to the at least one stacked memory device. 
     
     
         9 . The semiconductor package of  claim 1 , wherein the at least one stacked memory device is configured to merge calculated results from the neural network engine and inside of the at least one stacked memory device. 
     
     
         10 . The semiconductor package of  claim 1 , wherein the at least one stacked memory device is configured to provide the merged results to a user. 
     
     
         11 . The semiconductor package of  claim 1 , wherein the first calculation in the neural network engine and the second calculation in the at least one stacked memory device are performed in parallel. 
     
     
         12 . The semiconductor package of  claim 1 , wherein PIM circuit is configured to perform matrix-vector multiplication operation on the second portion of the input data and weights stored in a memory die of the at least one stacked memory device. 
     
     
         13 . The semiconductor package of  claim 1 , wherein PIM circuit is configured to divide the input data into the first portion and the second portion and is configured to the first portion to the neural network engine. 
     
     
         14 . The semiconductor package of  claim 1 , wherein PIM circuit is configured to receive a first calculated result from the neural network engine and a second calculated result inside of the PIM circuit and to merge the first calculated result and the second calculated result. 
     
     
         15 . The semiconductor package of  claim 1 , wherein PIM circuit is configured to receive the input data, weight and learning data through a plurality of through silicon vias (TSVs) extending through a plurality of memory dies stacked on the buffer die. 
     
     
         16 . A semiconductor package comprising:
 a data processor mounted on an interposer, the data processor including neural network engine; and   one or more stacked memory devices mounted on the interposer, at least one stacked memory device of the one or more stacked memory devices includes buffer die which includes a processor in memory (PIM) circuit,   wherein the PIM circuit is configured to receive learning data and weights from some of plurality of memory dies stacked on the buffer die, divide a feature vector extracted from an input data into a first portion and a second portion, to provide the first portion to the data processor, to receive a learned object recognition model from the processor, to perform a first calculation to apply the second portion and the weights to the learned object recognition model to generate a second object recognition result and to merge the second object recognition result and a first object recognition result generated by the neural network engine to provide a merged object recognition result to a user.   
     
     
         17 . The semiconductor package of  claim 16 , wherein the neural network engine is to provide the learned object recognition model to the PIM circuit when a similarity between a result of applying the learning data and the weights to the object recognition model and an expected value of the learning data is equal to or greater than a reference value. 
     
     
         18 . The semiconductor package of  claim 16 , wherein the neural network engine is configured to perform a second calculation to apply the first portion and the weights to the learned object recognition model to provide the first object recognition result to PIM circuit.