Neuromorphic system and operating method thereof
Abstract
A neuromorphic system includes an address translation device that translates an address corresponding to each of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address, and a plurality of synapse memories that store the synaptic weights based on the translation address. The translation address is generated such that at least two of synaptic weights corresponding to each of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories and such that at least two of synaptic weights corresponding to each of the presynaptic neurons are stored in different synapse memories.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A system for processing neural network comprising:
an address translation device configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address; and a plurality of synapse memories configured to store the plurality of synaptic weights based on the translation address, wherein the translation address is generated such that at least two of the plurality of synaptic weights corresponding to a same one of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories.
2 . A system for processing neural network comprising:
an address translation device configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address and read each of the plurality of synaptic weights using the translation address; and a plurality of synapse memories configured to store the plurality of synaptic weights, wherein the address translation device is further configured to read at least two of the plurality of synaptic weights corresponding to a same one of the postsynaptic neurons from different synapse memories of the plurality of synapse memories and reorder the at least two of the plurality of synaptic weights.Join the waitlist — get patent alerts
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