Systems and methods for manufacturing nano-electro-mechanical-system probes

Abstract

A method for implementing a transistor using multiple integrated probe tips is provided. The method comprises the steps of (1) providing a sample; (2) providing a microscope probe comprising a plurality of probe tips; (3) contacting a first outer probe tip of the plurality of probe tips to the sample, wherein he first outer probe tip is configured to act as a source terminal for a transistor; (4) contacting a second outer probe tip of the plurality of probe tips to the sample, wherein the second outer probe tip is configured to act as a drain terminal for the transistor; (5) using an inner probe tip of the plurality of probe tips as a gate terminal for the transistor; and (6) characterizing the sample with the plurality of probe tips.

What is claimed is: 
     
         1 . A method for implementing a transistor using multiple integrated probe tips, the method comprising the steps of:
 providing a sample;   providing a microscope probe comprising a plurality of probe tips;   contacting a first outer probe tip of the plurality of probe tips to the sample, wherein the first outer probe tip is configured to act as a source terminal for a transistor;   contacting a second outer probe tip of the plurality of probe tips to the sample, wherein the second outer probe tip is configured to act as a drain terminal for the transistor;   using an inner probe tip of the plurality of probe tips as a gate terminal for the transistor; and   characterizing the sample with the plurality of probe tips.   
     
     
         2 . The method of  claim 1 , wherein the inner probe tip makes soft contact with the sample. 
     
     
         3 . The method of  claim 1 , wherein the inner probe tip is in proximity to the sample. 
     
     
         4 . The method of  claim 1 , wherein the inner probe tip comprises a dielectric coating, and further wherein the dielectric coating is in contact with the sample. 
     
     
         5 . The method of  claim 1 , wherein the inner probe tip comprises a few nanometers of either high or low-k dielectric that is deposited at an apex of the inner probe tip. 
     
     
         6 . The method of  claim 1 , wherein the inner probe tip comprises a dielectric coating, and further wherein the dielectric coating is in proximity to the sample. 
     
     
         7 . The method of  claim 1 , wherein the sample comprises a 2D material. 
     
     
         8 . The method of  claim 7 , wherein the 2D material is graphene or molybdenum disulphide. 
     
     
         9 . The method of  claim 1 , wherein the sample comprises silicon substrate or gallium nitride. 
     
     
         10 . The method of  claim 1 , wherein the plurality of probe tips is used to perform output and transfer curves of the transistor. 
     
     
         11 . The method of  claim 1 , wherein the inner probe tip is configured to be shorter than both the first outer probe tip and the second outer probe tip. 
     
     
         12 . The method of  claim 11 , wherein there is an airgap or a gate capacitance between the inner probe tip and the sample. 
     
     
         13 . The method of  claim 12 , wherein the gate capacitance is varied by applying voltages to an actuation electrode that causes the inner probe to extend towards or retract from the sample.