Methods and apparatus to improve computing resource utilization

Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to improve computing resource utilization. An example apparatus includes an application specific sensor (AS) to monitor a workload of a platform, the workload executing on at least one general purpose central processing unit (CPU) of the platform, and a dynamic deployment module (DDM) to: in response to a workload performance threshold being satisfied, identify a bit stream capable of configuring a field programmable gate array (FPGA) to execute the workload, and configure the FPGA via the bit stream to execute at least a portion of the workload.

1 - 20 . (canceled) 
     
     
         21 - 32 . (canceled) 
     
     
         33 . An apparatus comprising:
 interface circuitry;   machine readable instructions; and   first processor circuitry to at least one of instantiate or execute the machine readable instructions to:   determine an application satisfies a performance metric;   determine whether a physically reprogrammable bitstream corresponding to the application is available in a local memory;   generate a parameter list based on (a) an application workload type corresponding to the application and (b) a target hardware type; and   cause the parameter list to be forwarded to a bitstream repository with a request for the physically reprogrammable bitstream that matches the parameter list.   
     
     
         34 . The apparatus as defined in  claim 33 , wherein the first processor circuitry is to configure second processor circuitry corresponding to the target hardware type with the physically reprogrammable bitstream to execute at least one task corresponding to the application. 
     
     
         35 . The apparatus as defined in  claim 34 , wherein the first processor circuitry is to cause at least one performance metric of the application to be improved by causing execution of the second processor circuitry corresponding to the target hardware type. 
     
     
         36 . The apparatus as defined in  claim 35 , wherein the at least one performance metric includes at least one of a workload latency, execution of the at least one task by the second processor circuitry corresponding to the target hardware type to reduce the workload latency. 
     
     
         37 . The apparatus as defined in  claim 33 , wherein the threshold performance metric includes at least one of a central processing unit (CPU) utilization, a memory utilization, or a traffic bandwidth. 
     
     
         38 . The apparatus as defined in  claim 33 , wherein the first processor circuitry is to cause a central processing unit (CPU) to stop executing the application when second processor circuitry corresponding to the target hardware type is configured with the physically reprogrammable bitstream to execute the application. 
     
     
         39 . The apparatus as defined in  claim 38 , wherein at least one of the CPU or the second processor circuitry corresponding to the target hardware type is located on at least one of a cloud-based computing platform or a stand-alone computing device. 
     
     
         40 . The apparatus as defined in  claim 33 , wherein second processor circuitry corresponding to the target hardware type is a field-programmable gate array (FPGA). 
     
     
         41 . The apparatus as defined in  claim 33 , wherein the first processor circuitry is to generate the parameter list in response to determining that the local memory does not include the physically reprogrammable bitstream corresponding to the application. 
     
     
         42 . A non-transitory machine readable storage medium comprising instructions that, when executed, cause first processor circuitry to at least:
 determine an application satisfies a performance metric;   determine whether a physically reprogrammable bitstream corresponding to the application is available in a local memory;   generate a parameter list based on (a) an application workload type corresponding to the application and (b) a target hardware type; and   cause the parameter list to be forwarded to a bitstream repository with a request for the physically reprogrammable bitstream that matches the parameter list.   
     
     
         43 . The machine readable storage medium as defined in  claim 42 , wherein the instructions, when executed, cause the first processor circuitry to configure second processor circuitry corresponding to the target hardware type with the physically reprogrammable bitstream to execute at least one task corresponding to the application. 
     
     
         44 . The machine readable storage medium as defined in  claim 43 , wherein the instructions, when executed, cause the first processor circuitry to cause at least one performance metric of the application to be improved by causing execution of the second processor circuitry corresponding to the target hardware type. 
     
     
         45 . The machine readable storage medium as defined in  claim 44 , wherein the instructions, when executed, cause the first processor circuitry to identify the at least one performance metric as at least one of a workload latency, execution of the at least one task by the second processor circuitry corresponding to the target hardware type to reduce the workload latency. 
     
     
         46 . The machine readable storage medium as defined in  claim 42 , wherein the instructions, when executed, cause the first processor circuitry to identify the threshold performance metric as at least one of a central processing unit (CPU) utilization, a memory utilization, or a traffic bandwidth. 
     
     
         47 . The machine readable storage medium as defined in  claim 42 , wherein the instructions, when executed, cause the first processor circuitry to cause a central processing unit (CPU) to stop executing the application when second processor circuitry corresponding to the target hardware type is configured with the physically reprogrammable bitstream to execute the application. 
     
     
         48 . The machine readable storage medium as defined in  claim 47 , wherein the instructions, when executed, cause the first processor circuitry to generate the parameter list in response to determining that the local memory does not include the physically reprogrammable bitstream corresponding to the application. 
     
     
         49 . A method comprising:
 determining, by executing an instruction with first processor circuitry, an application satisfies a performance metric;   determining, by executing an instruction with the first processor circuitry, whether a physically reprogrammable bitstream corresponding to the application is available in a local memory;   generating, by executing an instruction with the first processor circuitry, a parameter list based on (a) an application workload type corresponding to the application and (b) a target hardware type; and   causing, by executing an instruction with the first processor circuitry, the parameter list to be forwarded to a bitstream repository with a request for the physically reprogrammable bitstream that matches the parameter list.   
     
     
         50 . The method as defined in  claim 49 , further including configuring second processor circuitry corresponding to the target hardware type with the physically reprogrammable bitstream to execute at least one task corresponding to the application. 
     
     
         51 . The method as defined in  claim 50 , further including causing at least one performance metric of the application to be improved by causing execution of the second processor circuitry corresponding to the target hardware type. 
     
     
         52 . The method as defined in  claim 51 , further including identifying the at least one performance metric as at least one of a workload latency, execution of the at least one task by the second processor circuitry corresponding to the target hardware type to reduce the workload latency.