Memory controller and memory system for generating instruction set based on non-interleaving block group information

Abstract

Embodiments of the present invention include a memory controller including a buffer memory configured to store program data, an instruction set configurator configured to configure an instruction set describing a procedure for programming the program data stored in the buffer memory to target memory blocks, an instruction set performer configured to sequentially perform instructions in the instruction set and generate an interrupt at a time of completion of performance of a last instruction among the instructions, and a central processing unit configured to erase the program data stored in the buffer memory when the interrupt is received from the instruction set performer. The instruction set configurator may configure the instruction set differently according to whether a non-interleaving block group exists among the target memory blocks.

What is claimed is: 
     
         1 . A memory system comprising:
 a first die including a non-interleaving block group;   a second die including an interleaving block group; and   a memory controller configured to:   transmit first partial data of first data from a buffer memory to the first die to program the first partial data into the non-interleaving block group,   transmit, after transmitting the first partial data, second data from the buffer memory to the second die to program the second data into the interleaving block group,   transmit, after transmitting the second data, second partial data of the first data from the buffer memory to the first die to program the second partial data into the non-interleaving block group, and   erase, after transmitting the second partial data, the first and second data stored in the buffer memory.   
     
     
         2 . The memory system of  claim 1 , wherein the memory controller comprises:
 an instruction set configurator configured to configure an instruction set describing a procedure for sequentially programming the first and second data; and   an instruction set performer configured to sequentially perform instructions in the instruction set, to transmit the first and second data to the first and second dies.   
     
     
         3 . The memory system of  claim 2 ,
 wherein the instruction set performer generates an interrupt at a time of completion of performance of a last instruction among the instructions in the instruction set, and   wherein the last instruction is related to the second partial data.   
     
     
         4 . The memory system of  claim 3 , wherein the memory controller comprises a central processing unit configured to erase the first and second data stored in the buffer memory when the interrupt is received from the instruction set performer. 
     
     
         5 . The memory system of  claim 2 , wherein the instruction set configurator separately configures first instructions corresponding to the first partial data and second instructions corresponding to the second partial data. 
     
     
         6 . The memory system of  claim 5 , wherein the instruction set configurator configures third instructions corresponding to the second data separately from the first and second instructions. 
     
     
         7 . The memory system of  claim 6 , wherein the instruction set configurator configures the instruction set such that the second instructions are set to be performed after the third instructions. 
     
     
         8 . The memory system of  claim 5 , wherein the instruction set performer accesses the first die according to the first instructions, the second instructions, or a separate instruction that is not included in the instruction set, and holds the separate instruction before performance of the second instructions is completed. 
     
     
         9 . The memory system of  claim 1 ,
 wherein memory blocks of the non-interleaving block group are included in the same plane of the first die, and   wherein memory blocks of the interleaving block group are included in different planes of the second die.   
     
     
         10 . A memory system comprising:
 a memory device including first and second dies sharing a single channel, the first die including first and second memory blocks within a single plane of the first die, and the second die including a group of memory blocks within different planes of the second die;   a buffer configured to buffer first to third pieces of data; and   a controller configured to:   control the memory device to perform a program operation of sequentially storing the first to third pieces respectively into the first memory block, the group and the second memory block; and   remove the first to third pieces from the buffer upon completion of the program operation,   wherein the program operation is performed on the group according to a plane interleaving scheme.