Reducing corruption of communication in a wireless power transmission system

Abstract

An embodiment of the invention provides a method for reducing data corruption in a wireless power transmission system. Power is transmitted from a primary coil to a secondary coil by induction. The voltage induced on the secondary coil by induction is rectified. The change in current supplied to a load configured to be coupled to the wireless power transmission system is limited.

What is claimed is: 
     
         1 . A circuit comprising:
 a rectifier circuit coupled to a first current path;   a communication switch coupled to the first current path; and   a charge control circuit including:
 a charge control input coupled to the first current path; 
 a charge control output; 
 a transistor including a first terminal coupled to the charge control input, a second terminal coupled to the charge control output, and a control terminal; and 
 a first operational amplifier including a first input coupled to a second current path, a second input coupled to a voltage reference, and an output coupled to the control terminal of the transistor. 
   
     
     
         2 . The circuit of  claim 1 , wherein:
 the charge control circuit includes a current sensor; and   the first current path and the second current path are coupled to the current sensor.   
     
     
         3 . The circuit of  claim 1 , wherein:
 a load is coupled to the charge control output.   
     
     
         4 . The circuit of  claim 1 , wherein:
 the charge control circuit includes a second operation amplifier and a first resistor; and   the second operational amplifier includes a first input coupled to the second current path, a second input, and an output coupled to a first terminal of the first resistor.   
     
     
         5 . The circuit of  claim 4 , further including:
 a capacitor including a first terminal coupled to a second terminal of the first resistor, and a second terminal of the capacitor coupled to a ground terminal.   
     
     
         6 . The circuit of  claim 5 , wherein:
 the first resistor and the capacitor are configured as a low-pass filter.   
     
     
         7 . The circuit of  claim 5 , wherein:
 the second terminal of the first resistor and the first terminal of the capacitor are coupled to the second input of the first operational amplifier.   
     
     
         8 . The circuit of  claim 5 , wherein:
 the output of the second operational amplifier is coupled to a first terminal of a second resistor;   the second input of the second operational amplifier is coupled to a second terminal of the second resistor;   the second input of the second operational amplifier and the second terminal of the second resistor is coupled to a first terminal of a third resistor; and   a second terminal of the third resistor is coupled to the ground terminal.   
     
     
         9 . The circuit of  claim 8 , wherein:
 the charge control circuit includes a fourth resistor; and   a first terminal of the fourth resistor is coupled to the second current path and a first input of the second operational amplifier.   
     
     
         10 . The circuit of  claim 1 , wherein:
 the charge control circuit includes a current source coupled to the first terminal of the transistor and the control terminal of the transistor.   
     
     
         11 . A receiver comprising:
 a rectifier circuit coupled to a first current path;   a communication switch coupled to the first current path; and   a charge control circuit including:
 a charge control input coupled to the first current path; 
 a charge control output; 
 a transistor including a first terminal coupled to the charge control input, a second terminal coupled to the charge control output, and a control terminal; and 
 an operational amplifier including a first input coupled to a second current path, a second input coupled to a voltage reference, and an output coupled to the control terminal of the transistor. 
   
     
     
         12 . The receiver of  claim 11 , wherein:
 a load is coupled to the charge control output.   
     
     
         13 . The receiver of  claim 11 , wherein:
 the charge control circuit includes a current sensor; and   the first current path and the second current path are coupled to the current sensor.   
     
     
         14 . The receiver of  claim 13 , wherein:
 the charge control circuit includes a first resistor and a second resistor;   a first terminal of the first resistor is coupled to the current sensor;   a second terminal of the first resistor is coupled to a first terminal of the second resistor; and   a second terminal of the second resistor is coupled to a ground terminal.   
     
     
         15 . The receiver of  claim 14 , wherein:
 the charge control circuit includes an analog-to-digital converter (ADC); and   an input of the ADC is coupled to the current sensor and the first terminal of the first resistor.   
     
     
         16 . The receiver of  claim 15 , wherein:
 the charge control circuit includes a digital-to-analog converter (DAC);   an output of the ADC is coupled to an input of the DAC;   an output of the DAC is coupled to the first input of the operational amplifier; and   the second input of the operational amplifier is coupled to the second terminal of the first resistor and the first terminal of the second resistor.   
     
     
         17 . A system comprising:
 a transmitter; and   a receiver including:
 a rectifier circuit coupled to a first current path; 
 a communication switch coupled to the first current path; and 
 a charge control circuit including:
 a charge control input coupled to the first current path; 
 a charge control output; 
 a transistor including a first terminal coupled to the charge control input, a second terminal coupled to the charge control output, and a control terminal; and 
 a first operational amplifier including a first input coupled to a second current path, a second input coupled to a voltage reference, and an output coupled to the control terminal of the transistor. 
 
   
     
     
         18 . The system of  claim 17 , wherein:
 the charge control circuit includes a second operation amplifier and a first resistor; and   the second operational amplifier includes a first input coupled to the second current path, a second input, and an output coupled to a first terminal of the first resistor.   
     
     
         19 . The system of  claim 17 , wherein:
 the charge control circuit includes an analog-to-digital converter (ADC) and a current sensor;   the current sensor is coupled to the first current path and the second current path; and   an input of the ADC is coupled to the current sensor.   
     
     
         20 . The system of  claim 19 , further including:
 the charge control circuit includes a digital-to-analog converter (DAC); and   an output of the ADC is coupled to an input of the DAC; an output of the DAC is coupled to the first input of the first operational amplifier.