Display panel

Abstract

A display panel is provided. The display panel includes a base substrate, a plurality of subpixels. A respective subpixel includes a respective light emitting element and a respective pixel driving circuit. The respective pixel driving circuit includes a third transistor; and a storage capacitor including a first capacitor electrode in a first conductive layer and a second capacitor electrode in a second conductor layer. The second conductive layer is on a side of the first conductive layer away from the base substrate. The second capacitor electrode includes an extension extending away from an electrode main body of the second capacitor electrode. An orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor of the respective pixel driving circuit on the base substrate.

What is claimed is: 
     
         1 . A display panel, comprising a base substrate, a plurality of subpixels, a respective subpixel comprising a respective light emitting element and a respective pixel driving circuit;
 wherein the respective pixel driving circuit comprises:   a third transistor; and   a storage capacitor comprising a first capacitor electrode in a first conductive layer and a second capacitor electrode in a second conductor layer;   wherein the second conductive layer is on a side of the first conductive layer away from the base substrate;   the second capacitor electrode comprises an extension extending away from an electrode main body of the second capacitor electrode; and   an orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor of the respective pixel driving circuit on the base substrate.   
     
     
         2 . The display panel of  claim 1 , wherein the third transistor comprises a first gate electrode and a second gate electrode;
 an orthographic projection of the first gate electrode on the base substrate overlaps with an orthographic projection of a first channel part of the active layer of the third transistor on the base substrate;   an orthographic projection of the second gate electrode on the base substrate overlaps with an orthographic projection of a second channel part of the active layer of the third transistor on the base substrate;   the active layer of the third transistor further comprises a portion connecting the first channel part and the second channel part; and   the orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of the portion connecting the first channel part and the second channel part on the base substrate.   
     
     
         3 . The display panel of  claim 1 , further comprising a first signal line layer on a side of the storage capacitor away from the base substrate;
 wherein multiple second capacitor electrodes respectively from multiple pixel driving circuits are sequentially connected to each other along a first direction;   the first signal line layer comprises a plurality of first high voltage signal lines respectively along a first direction; and   a respective one of the plurality of first high voltage signal lines is connected to the second capacitor electrode.   
     
     
         4 . The display panel of  claim 1 , wherein the extension comprises a first extension part along a second direction and a second extension part along a first direction;
 the first extension part connects the second extension part with the electrode main body of the second capacitor electrode; and   an orthographic projection of the second extension part on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate.   
     
     
         5 . The display panel of  claim 4 , wherein the second extension part comprises a shielding portion and a non-shielding portion;
 an orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate;   an orthographic projection of the non-shielding portion on the base substrate is non-overlapping with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate; and   a line width of the shielding portion is greater than a line width of the non-shielding portion.   
     
     
         6 . The display panel of  claim 4 , wherein the respective pixel driving circuit further comprises a driving transistor, and a node connecting line connecting a drain electrode of the third transistor with a gate electrode of the driving transistor;
 wherein the drain electrode of the third transistor is connected to the gate electrode of the driving transistor;   a source electrode of the third transistor is connected to a drain electrode of the driving transistor; and   an orthographic projection of the first extension part on a line extending along the second direction at least partially overlaps with an orthographic projection of the node connecting line on the line.   
     
     
         7 . The display panel of  claim 6 , further comprising a plurality of data lines;
 wherein the first extension part is between the node connecting line and a respective data line of the plurality of data lines.   
     
     
         8 . The display panel of  claim 1 , further comprising a plurality of gate lines;
 wherein a respective gate line of the plurality of gate lines comprises a plurality of metal blocks spaced apart from each other in a first conductive layer, and a metal line along a first direction in a first signal line layer, the metal line along the first direction being connected to the plurality of metal blocks through vias, respectively.   
     
     
         9 . The display panel of  claim 8 , wherein a respective metal block of the plurality of metal blocks has a L shape;
 an orthographic projection of a first channel part of the active layer of the third transistor on the base substrate overlaps with an orthographic projection of a first metal portion of the respective metal block of the plurality of metal blocks on the base substrate;   an orthographic projection of a second channel part of the active layer of the third transistor on the base substrate overlaps with an orthographic projection of a second metal portion of the respective metal block of the plurality of metal blocks on the base substrate; and   the first metal portion and the second metal portion are a first gate electrode and a second gate electrode of the third transistor.   
     
     
         10 . The display panel of  claim 1 , further comprising:
 a plurality of first reset signal lines respectively along a first direction in a semiconductor material layer; and   a plurality of second reset signal lines respectively along a second direction in a second signal line layer;   wherein the plurality of first reset signal lines respectively cross over the plurality of second reset signal lines;   a respective one of the plurality of first reset signal lines is connected to at least multiple ones of the plurality of second reset signal lines through vias; and   a respective one of the plurality of second reset signal lines is connected to at least multiple ones of the plurality of first reset signal lines through vias.   
     
     
         11 . The display panel of  claim 1 , further comprising a plurality of second low voltage signal lines respectively along a second direction in a second signal line layer;
 wherein the plurality of second low voltage signal lines are electrically connected to a cathode of a light emitting element.   
     
     
         12 . The display panel of  claim 1 , further comprising:
 a plurality of first high voltage signal lines respectively extending along the first direction in a first signal line layer; and   a plurality of second high voltage signal lines respectively extending along a second direction in a second signal line layer;   wherein the plurality of first high voltage signal lines respectively cross over the plurality of second high voltage signal lines;   a respective one of the plurality of first high voltage signal lines is connected to at least multiple ones of the plurality of second high voltage signal lines through vias; and   a respective one of the plurality of second high voltage signal lines is connected to at least multiple ones of the plurality of first high voltage signal lines through vias.   
     
     
         13 . The display panel of  claim 12 , wherein a respective one of the plurality of first high voltage signal lines comprises:
 a main body extending along a first direction;   a protrusion protruding away from the main body along a second direction, and   wherein the protrusion is a portion where the respective one of the plurality of second high voltage signal line is connected to a respective one of the plurality of first high voltage signal lines through one or more vias.   
     
     
         14 . The display panel of  claim 12 , wherein the respective pixel driving circuit further comprises a driving transistor, and a node connecting line connecting a drain electrode of the third transistor with a gate electrode of the driving transistor;
 wherein the drain electrode of the third transistor is connected to the gate electrode of the driving transistor;   a source electrode of the third transistor is connected to a drain electrode of the driving transistor; and   an orthographic projection of the respective one of the plurality of second high voltage signal lines on the base substrate covers an orthographic projection of the node connecting line on the base substrate.   
     
     
         15 . The display panel of  claim 12 , wherein an orthographic projection of the respective one of the plurality of second high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of at least one gate electrode of the third transistor on the base substrate. 
     
     
         16 . The display panel of  claim 1 , wherein the display panel comprises:
 a plurality of light emitting elements; and   an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements;   wherein the interconnected first voltage supply network comprises signal lines in a display area of the display panel, the display area being at least partially surrounded by a peripheral area;   the signal lines comprise a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer;   the display panel further comprises a planarization layer between the first signal line layer and the second signal line layer; and   the plurality of first signal lines are electrically connected to the plurality of second signal lines.   
     
     
         17 . The display panel of  claim 16 , wherein the interconnected first voltage supply network comprises:
 a plurality of first-first voltage signal lines respectively along a first direction; and   a plurality of second-first voltage signal lines respectively along a second direction;   wherein the plurality of first-first voltage signal lines respectively cross over the plurality of second-first voltage signal lines.   
     
     
         18 . The display panel of  claim 17 , wherein the interconnected first voltage supply network comprises a first sub-network formed by the plurality of first-first voltage signal lines and a second sub-network formed by the plurality of second-first voltage signal lines. 
     
     
         19 . The display panel of  claim 17 , wherein a respective one of the plurality of first-first voltage signal lines is connected to at least multiple ones of the plurality of second-first voltage signal lines; and
 a respective one of the plurality of second-first voltage signal lines is connected to at least multiple ones of the plurality of first-first voltage signal lines.   
     
     
         20 . The display panel of  claim 17 , wherein the plurality of first-first voltage signal lines and the plurality of second-first voltage signal lines interconnect through first vias respectively extending through the planarization layer, at least some of the first vias being in the display area;
 a respective one of the plurality of first-first voltage signal lines is connected to at least multiple ones of the plurality of second-first voltage signal lines respectively through multiple first vias extending through the planarization layer; and   a respective one of the plurality of second-first voltage signal lines is connected to at least multiple ones of the plurality of first-first voltage signal lines respectively through multiple first vias extending through the planarization layer.