Multibit shift instruction

Abstract

An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

1 . An article of manufacture comprising a non-transitory machine-readable medium, the medium comprising instructions, the instructions, when read and executed by a processor, cause the processor to execute a shift instruction, the shift instruction to cause a source data in memory to be shifted left or shifted right, the source data including a plurality of source words, the shift instruction to include a source parameter to identify the source data, the shift instruction to include a bit size parameter to identify a specified number of bits by which the source data is to be shifted, through:
 a shift of a first source word of the source data by the specified number of bits to yield a first intermediate word;   a shift of a second source word of the source data by the specified number of bits to yield a second intermediate word and a first set of shifted-out bits; and   execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.   
     
     
         2 . The article of manufacture of  claim 1 , wherein the instructions are to cause the processor to execute the shift instruction through:
 a shift of a third source word of the source data by the specified number of bits to yield a third intermediate word and a second set of shifted-out bits; and   execution of a logical OR operation on the second intermediate word and the second set of shifted-out bits to yield a second result word.   
     
     
         3 . The article of manufacture of  claim 1 , wherein the instructions are to cause the processor to execute the shift instruction through:
 a shift of a last source word of the source data by the specified number of bits to yield a last result word and a last set of shifted-out bits;   execution of a logical OR operation on a next-to-last intermediate word and the last set of shifted-out bits to yield a next-to-last result word.   
     
     
         4 . The article of manufacture of  claim 1 , wherein the execution of the logical OR operation on the first intermediate word and the first set of shifted-out bits is to be performed in place on the first intermediate word to cause the first intermediate word to be the first result word. 
     
     
         5 . The article of manufacture of  claim 1 , wherein the logical OR operation is to apply the first set of shifted-out bits as most significant bits. 
     
     
         6 . The article of manufacture of  claim 1 , wherein the specified number of bits is a plurality of bits less than a size of a word of the source words. 
     
     
         7 . The article of manufacture of  claim 1 , wherein:
 the shift instruction is to cause the source data in memory to be shifted left;   the first source word is more significant than the second source word; and   the shift of the first source word to yield the first intermediate word is to be performed before the shift of the second source word.   
     
     
         8 . A method, comprising:
 executing a shift instruction, the shift instruction to cause a source data in memory to be shifted left or shifted right, the source data including a plurality of source words, the shift instruction to include a source parameter to identify the source data, the shift instruction to include a bit size parameter of a specified number of bits by which the source data is to be shifted; and   executing the shift instruction by:
 executing a logical shift function of a first source word of source data by the specified number of bits to yield a first intermediate word; 
 executing a logical shift function of a second source word of the source data by the specified number of bits to yield a second intermediate word and a first set of shifted-out bits; and 
 executing of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word. 
   
     
     
         9 . The method of  claim 8 , comprising executing the shift instruction by:
 executing a shift of a third source word of the source data by the specified number of bits to yield a third intermediate word and a second set of shifted-out bits; and   executing a logical OR operation on the second intermediate word and the second set of shifted-out bits to yield a second result word.   
     
     
         10 . The method of  claim 8 , comprising executing the shift instruction by:
 execution of a shift of a last source word of the source data by the specified number of bits to yield a last result word and a last set of shifted-out bits;   execution of a logical OR operation on a next-to-last intermediate word and the last set of shifted-out bits to yield a next-to-last result word.   
     
     
         11 . The method of  claim 8 , comprising executing the logical OR operation on the first intermediate word and the first set of shifted-out bits in place on the first intermediate word to cause the first intermediate word to be the first result word. 
     
     
         12 . The method of  claim 8 , comprising applying the logical OR operation with the first set of shifted-out bits as most significant bits. 
     
     
         13 . The method of  claim 8 , wherein the specified number of bits is a plurality of bits less than a size of a word of the source words. 
     
     
         14 . The method of  claim 8 , wherein:
 the shift instruction is to shift left the source data in memory;   the first source word is more significant than the second source word; and   the method includes shifting the first source word to yield the first intermediate word before shifting the second source word.   
     
     
         15 . A microcontroller, comprising:
 a source register, the source register of a capacity of a plurality of source words;   a destination register, the destination register of a capacity of a plurality of destination words; and   a processor to execute a shift instruction to shift contents of the source register and store a result in the destination register, the shift instruction comprising an identifier of a specified number of bits by which the source register is to be shifted, the execution to include iterative shifting of words of the source register, including:
 a shift of an Nth word of the plurality of source words to yield an Nth intermediate word and an Nth set of shifted-out bits; 
 a shift of an (N-1)th word of the plurality of source words to yield an (N-1)th intermediate word and an (N-1)th set of shifted-out bits; and 
 execution of a logical OR operation on the (N-1)th intermediate word and the Nth set of shifted-out bits to yield an (N-1)th destination word for the destination register. 
   
     
     
         16 . The microcontroller of  claim 15 , wherein the processor is to shift the Nth word, shift the (N-1)th word, and perform the logical OR operation on the (N-1)th intermediate word and the Nth set of shifted-out bits to yield the (N-1)th destination word for at least intervening words of the plurality of source words in the source register between a first word and a last word of the plurality of source words. 
     
     
         17 . The microcontroller of  claim 15 , wherein the processor is to execute the shift instruction through:
 shift a last source word of the source register by the specified number of bits to yield a last destination result word and a last set of shifted-out bits;   execution of a logical OR operation on a next-to-last intermediate word and the last set of shifted-out bits to yield a next-to-last destination word.   
     
     
         18 . The microcontroller of  claim 15 , wherein the execution of the logical OR operation on (N-1)th intermediate word and the Nth set of shifted-out bits is to be performed in place on the (N-1)th intermediate word to cause the (N-1)th intermediate word to be the (N-1)th destination word. 
     
     
         19 . The microcontroller of  claim 15 , wherein:
 the Nth source word is more significant than the (N-1)th source word;   the shift instruction is a right shift instruction; and   the shift of the Nth word of the source register to yield the Nth intermediate word is to be performed after execution of the shift of the (N-1)th word of the source register.   
     
     
         20 . The microcontroller of  claim 15 , wherein:
 the Nth source word is less significant than the (N-1)th source word;   the shift instruction is a left shift instruction; and   the shift of the Nth word of the source register to yield the Nth intermediate word is to be performed after execution of the shift of the (N-1)th word of the source register.