Voltage threshold prediction-based memory management

Abstract

A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.

What is claimed is: 
     
         1 . A method, comprising:
 predicting a shift in a voltage threshold associated with a set of memory cells responsive to performance of a first memory operation;   performing a second memory operation involving the set of memory cells using a first voltage in response to determining that the quantity of bits exceeds a first threshold quantity of bits based on the predicted shift in the voltage associated with the set of memory cells; or   performing the second memory operation involving the set of memory cells using a second voltage in response to determining that the quantity of bits is below the threshold quantity of bits for the set of memory cells based on the predicted shift in the voltage associated with the set of memory cells.   
     
     
         2 . The method of  claim 1 , further comprising performing the first memory operation using a voltage that is different than the first voltage and the second voltage. 
     
     
         3 . The method of  claim 1 , further comprising refraining from using the first voltage in response to determining that the quantity of bits is below the threshold quantity of bits for the set of memory cells. 
     
     
         4 . The method of  claim 1 , further comprising refraining from using the second voltage in response to determining that the quantity of bits is above the threshold quantity of bits for the set of memory cells. 
     
     
         5 . The method of  claim 1 , wherein the set of memory cells comprise a word line of a NAND memory device. 
     
     
         6 . The method of  claim 1 , comprising determining the threshold quantity of bits for the set of memory cells based on a particular memory cell or sub-set of memory cells that is in a particular physical location within the set of memory cells. 
     
     
         7 . An apparatus, comprising:
 a processing device configured to:
 perform, using a first voltage, a first memory operation that targets at least one memory cell within a set of memory cells to:
 determine a first threshold quantity of bits for the set of memory cells, and 
 determine a second threshold quantity of bits for the set of memory cells; 
 
 predict a shift in a voltage threshold associated with the set of memory cells based on performance of the first memory operation using the first threshold voltage that targets at least the one memory cell within the set of memory cells; 
 determine a second threshold voltage to be utilized for a second memory operation based on a comparison between the determined first threshold quantity of bits and the second threshold quantity of bits and the predicted shift in the voltage associated with the set of memory cells. 
   
     
     
         8 . The apparatus of  claim 7 , wherein the processing device is further configured to perform a second memory operation using the second threshold voltage. 
     
     
         9 . The apparatus of  claim 7 , wherein the second threshold voltage is greater than the first threshold voltage when the determined quantity of bits is greater than the first threshold quantity of bits. 
     
     
         10 . The apparatus of  claim 7 , wherein the second threshold voltage is less than the first threshold voltage when the determined quantity of bits is less than the second threshold quantity of bits. 
     
     
         11 . The apparatus of  claim 7 , wherein the processing device is configured to determine a plurality of subsequent threshold voltages to be greater than the first threshold voltage when the determined quantity of bits is greater than the first threshold quantity of bits. 
     
     
         12 . The apparatus of  claim 7 , wherein the processing device is configured to determine a plurality of subsequent threshold voltages to be less than the first threshold voltage when the determined quantity of bits is less than the second threshold quantity of bits. 
     
     
         13 . The apparatus of  claim 7 , wherein the processing device is configured to:
 perform only positive read offsets when the determined quantity of bits is greater than the first threshold quantity of bits, and   perform only negative read offsets when the determined quantity of bits is less than the second threshold quantity of bits.   
     
     
         14 . A non-transitory computer-readable medium storing instruction that, when executed by a processing device, cause the processing device to:
 perform a first memory operation involving a set of memory cells using a first threshold voltage to target a particular memory cell of the set of memory cells;   determine a quantity of bits of the set of memory cells based on the first memory operation using the first threshold voltage;   predict a shift in a voltage threshold associated with the set of memory cells based on performance of the first memory operation involving the set of memory cells using the first threshold voltage; and   perform memory operations involving the set of memory cells using a set of threshold voltages based on the predicted shift in the voltage threshold associated with the set of memory cells based on performance of the first memory operation involving the set of memory cells using the first threshold voltage.   
     
     
         15 . The medium of  claim 14 , wherein the processing device is configured to execute the instructions to:
 refrain from using negative offsets when the determined quantity of bits is greater than the upper bit count threshold, or   refrain from using positive offsets when the determined quantity of bits is less than the lower bit count threshold.   
     
     
         16 . The medium of  claim 14 , wherein the processing device is configured to execute the instructions to determine an upper bit count threshold and a lower bit count threshold for the set of memory cells based on the first threshold voltage. 
     
     
         17 . The medium of  claim 14 , wherein the set of threshold voltages comprises:
 a set of positive offsets when the determined quantity of bits is greater than the upper bit count threshold;   a set of negative offsets when the determined quantity of bits is less than the lower bit count threshold, or   a combination of positive and negative offsets when the determined quantity of bits is between the upper bit count threshold and the lower bit count threshold.   
     
     
         18 . The medium of  claim 16 , wherein the processing device is configured to execute the instructions to alter the upper bit count threshold and the lower bit count threshold based on a designated read level as part of performing the memory operations. 
     
     
         19 . The medium of  claim 18 , wherein the processing device is configured to execute the instructions to alter the upper bit count threshold and the lower bit count threshold by
 increasing the upper bit count threshold and the lower bit count threshold when the first threshold voltage is lowered to a second threshold voltage, or   decreasing the upper bit count threshold and the lower bit count threshold when the first threshold voltage is increased to a third threshold voltage.   
     
     
         20 . The medium of  claim 14 , wherein the processing device is configured to execute the instructions to perform a read operation as part of performance of the first memory operation.