Low power memory device with column and row line switches for specific memory cells

Abstract

A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

What is claimed is: 
     
         1 . A memory device, comprising:
 a plurality of word lines;   a plurality of row word lines; and   a plurality of memory blocks, each of the memory blocks comprising a plurality of memory units, each of the memory units comprising: 
 a plurality of memory cell groups, each of the memory cell groups comprising a plurality of memory cells; 
 at least one bit line; 
 a column word line; 
 a plurality of column switches, each of the column switches having a control terminal coupled to the column word line; and 
 a plurality of row switches, each of the row switches having a control terminal coupled to a different one of the plurality of row word lines; 
 wherein each of the column switches and each of the row switches are coupled in series between the at least one bit line and the plurality of memory cells of one of the memory cell groups. 
   
     
     
         2 . The memory device of  claim 1 , wherein the plurality of column switches and the plurality of row switches are transistors. 
     
     
         3 . A memory device, comprising:
 a plurality of word lines; and   a plurality of memory blocks, each of the memory blocks comprising a plurality of memory units, each of the memory units comprising: 
 a plurality of memory cell groups, each of the memory cell groups comprising a plurality of memory cells; 
 at least one bit line; 
 a column word line; and 
 a plurality of column switches, each of the column switches having a control terminal coupled to the column word line, a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line, 
 wherein the column word lines of the memory units of the corresponding memory block are grouped to control the column switches of the corresponding memory block. 
   
     
     
         4 . The memory device of  claim 3 , wherein the plurality of column switches are transistors.