Configurable capacitor

Abstract

A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration.

1 . An electronic device comprising:
 a semiconductor substrate including a first integrally formed capacitor having first and second terminals formed at a bottom surface of the semiconductor substrate, the semiconductor substrate including a second integrally formed capacitor having third and fourth terminals formed at the bottom surface of the semiconductor substrate; and   an interconnect board attached to the semiconductor substrate and including:
 first, second, third and fourth electrical interconnects formed at a first surface wherein the first electrical interconnect is electrically connected to the first terminal, the second electrical interconnect is electrically connected to the second terminal, the third electrical interconnect is electrically connected to the third terminal and the fourth electrical interconnect is electrically connected to the fourth terminal; 
 a plurality of second electrical interconnects formed at a second surface opposite the first surface; and 
 a plurality of electrical conductors coupling the first, second, third and fourth electrical interconnects to two of the second electrical interconnects. 
   
     
     
         2 . The electronic device of  claim 1 , wherein the plurality of electrical conductors couple the first capacitor in parallel with the second capacitor. 
     
     
         3 . The electronic device of  claim 1 , wherein the plurality of electrical conductors couple the first capacitor in series with the second capacitor. 
     
     
         4 . The electronic device of  claim 1 , wherein the interconnect board comprises a printed circuit board. 
     
     
         5 . The electronic device of  claim 1 , wherein the plurality of second electrical interconnects comprise spherical interconnects arranged to be soldered to a separate electronic device. 
     
     
         6 . The electronic device of  claim 1 , wherein the first electrical interconnect is electrically connected to the first terminal, the second electrical interconnect is electrically connected to the second terminal, the third electrical interconnect is electrically connected to the third terminal and the fourth electrical interconnect is electrically connected to the fourth terminal via soldered interfaces. 
     
     
         7 . An electronic device comprising:
 a substrate including a plurality of integrally formed capacitors, each capacitor having respective electrical terminals formed at a bottom surface of the substrate; and   an interconnect board attached to the substrate and including:
 a plurality of first electrical interconnects formed at a first surface and electrically coupled to the electrical terminals; 
 a plurality of second electrical interconnects formed at a second surface opposite the first surface; and 
 a plurality of electrical conductors coupling at least two of the integrally formed capacitors together. 
   
     
     
         8 . The electronic device of  claim 7 , wherein the plurality of electrical conductors couple the at least two integrally formed capacitors together in parallel. 
     
     
         9 . The electronic device of  claim 7 , wherein the plurality of electrical conductors couple the at least two integrally formed capacitors together in series. 
     
     
         10 . The electronic device of  claim 7 , wherein the interconnect board comprises a printed circuit board. 
     
     
         11 . The electronic device of  claim 7 , wherein the plurality of second electrical interconnects comprise spherical interconnects arranged to be soldered to a separate electronic device. 
     
     
         12 . The electronic device of  claim 7 , wherein the plurality of first electrical interconnects are electrically coupled to the electrical terminals via soldered interfaces. 
     
     
         13 . A method of making an electronic device, the method comprising:
 forming a substrate including a plurality of integral capacitors, each capacitor having respective electrical terminals disposed at a bottom surface of the substrate; and   forming an interconnect board and attaching the interconnect board to the substrate, wherein the interconnect board comprises:
 a plurality of first electrical interconnects disposed at a first surface and electrically coupled to the electrical terminals; 
 a plurality of second electrical interconnects disposed at a second surface opposite the first surface; and 
 a plurality of electrical conductors arranged to couple at least two of the integral capacitors together. 
   
     
     
         14 . The method of  claim 13 , wherein the plurality of electrical conductors couple a first capacitor of the plurality of integral capacitors in parallel with a second capacitor of the plurality of integral capacitors. 
     
     
         15 . The method of  claim 13 , wherein the plurality of electrical conductors couple a first capacitor of the plurality of integral capacitors in series with a second capacitor of the plurality of integral capacitors. 
     
     
         16 . The method of  claim 13 , wherein the interconnect board comprises a printed circuit board. 
     
     
         17 . The method of  claim 13 , wherein the plurality of second electrical interconnects comprise spherical interconnects arranged to be soldered to a separate electronic device. 
     
     
         18 . The method of  claim 13 , wherein the plurality of first electrical interconnects are electrically coupled to the electrical terminals via soldered interfaces. 
     
     
         19 . The method of  claim 13 , wherein the interconnect board is a first interconnect board arranged to couple a first and a second capacitor of the plurality of integral capacitors in parallel, and wherein the substrate is configured to be attached to a second interconnect board arranged to couple the first and the second capacitors of plurality of integral capacitors in series. 
     
     
         20 . The method of  claim 13 , wherein the substrate further comprises an inductor.