Semiconductor device, battery protection circuit, and power management circuit

Abstract

A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.

1 . A semiconductor device of chip-size package type that is face-down mountable, the semiconductor device comprising:
 a semiconductor layer; and   N vertical MOS transistors in the semiconductor layer, where N is an integer greater than or equal to three, wherein   each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor,   the semiconductor layer includes a semiconductor substrate,   the semiconductor substrate functions as a common drain region for the N vertical MOS transistors,   for each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor, and   for each of the N vertical MOS transistors, the surface area of the vertical MOS transistor in a plan view of the semiconductor layer is proportional to a square of the maximum specified current of the vertical MOS transistor.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein
 for each of the N vertical MOS transistors, a conduction resistance when the maximum specified current flows is inversely proportional to the square of the maximum specified current of the vertical MOS transistor.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein
 one of the N vertical MOS transistors is a specific vertical MOS transistor whose maximum specified current is equal to a sum of maximum specified currents of K vertical MOS transistors among the N vertical MOS transistors, where K is an integer greater than or equal to two and less than or equal to N−1.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein
 the N vertical MOS transistors include at least one specific vertical MOS transistor the one or more source pads of which consist of a single source pad, and   the gate pad and the single source pad included in each of the at least one specific vertical MOS transistor are circular in a plan view of the semiconductor layer, and among the gate pad and the one or more source pads included in each of the N vertical MOS transistors, there is no gate pad or source pad that is significantly smaller in surface area than either of the gate pad or the single source pad included in each of the at least one specific vertical MOS transistor.   
     
     
         5 . The semiconductor device according to  claim 1 , wherein
 the semiconductor device is rectangular in a plan view of the semiconductor layer, and   in each of one or more current paths defined by specifications, a first inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at an inlet or an outlet of the current path and a second inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at the outlet or the inlet of the current path are adjacent to each other in a plan view of the semiconductor layer.   
     
     
         6 . The semiconductor device according to  claim 5 , wherein
 the semiconductor device has a shape of a non-square rectangle in a plan view of the semiconductor layer, and   in a plan view of the semiconductor layer, in each of the one or more current paths, a boundary line between the first inlet/outlet vertical MOS transistor and the second inlet/outlet vertical MOS transistor is parallel to a longer side of the semiconductor device.   
     
     
         7 . The semiconductor device according to  claim 5 , wherein
 in a plan view of the semiconductor layer, in each of the one or more current paths, a boundary line between the first inlet/outlet vertical MOS transistor and the second inlet/outlet vertical MOS transistor is not parallel to any of four sides of the semiconductor device.   
     
     
         8 . The semiconductor device according to  claim 5 , wherein
 in a plan view of the semiconductor layer, in each of the one or more current paths, a boundary line between the first inlet/outlet vertical MOS transistor and the second inlet/outlet vertical MOS transistor consists of alternately connected (i) one or more line segments parallel to a first side among four sides of the semiconductor device and (ii) one or more line segments parallel to a second side among the four sides that is orthogonal to the first side.   
     
     
         9 . The semiconductor device according to  claim 1 , wherein
 in a first current path defined by specifications, a first inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at an inlet or an outlet of the first current path and a second inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at the outlet or the inlet of the first current path are adjacent to each other in a plan view of the semiconductor layer,   in a second current path defined by the specifications, the first inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at an inlet or an outlet of the second current path and a third inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at the outlet or the inlet of the second current path are adjacent to each other in a plan view of the semiconductor layer,   in a third current path defined by the specifications, the second inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at an inlet or an outlet of the third current path and the third inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at the outlet or the inlet of the third current path are adjacent to each other in a plan view of the semiconductor layer, and   the gate pad of the third inlet/outlet vertical MOS transistor is located on an extension of a boundary line between the first inlet/outlet vertical MOS transistor and the second inlet/outlet vertical MOS transistor.   
     
     
         10 . The semiconductor device according to  claim 1 , wherein
 in a first current path defined by specifications, a first inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at an inlet or an outlet of the first current path and a second inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at the outlet or the inlet of the first current path are adjacent to each other in a plan view of the semiconductor layer,   in a second current path defined by the specifications, the second inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at an inlet or an outlet of the second current path and a third inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at the outlet or the inlet of the second current path are adjacent to each other in a plan view of the semiconductor layer,   a current path defined by the first inlet/outlet vertical MOS transistor and the third inlet/outlet vertical MOS transistor does not correspond to any of current paths defined by the specifications,   the first inlet/outlet vertical MOS transistor and the third inlet/outlet vertical MOS transistor are adjacent to each other in a plan view of the semiconductor layer, and   the gate pad of the third inlet/outlet vertical MOS transistor is located nearer to a boundary line between the first inlet/outlet vertical MOS transistor and the third inlet/outlet vertical MOS transistor than to a boundary line between the second inlet/outlet vertical MOS transistor and the third inlet/outlet vertical MOS transistor.   
     
     
         11 . The semiconductor device according to  claim 1 , further comprising:
 a drain pad on an upper surface of the semiconductor layer and electrically connected to the semiconductor substrate.   
     
     
         12 . A battery protection circuit comprising:
 the semiconductor device according to  claim 1 ;   a first terminal connected to the one or more source pads of a single terminal-connected vertical MOS transistor among the N vertical MOS transistors included in the semiconductor device; and   N−1 battery cells each including a first electrode connected to the one or more source pads of a different one of N−1 vertical MOS transistors among the N vertical MOS transistors included in the semiconductor device excluding the single terminal-connected vertical MOS transistor, the first electrode being one of a positive electrode or a negative electrode, and   each of the first electrodes included in the N−1 battery cells has a same polarity.   
     
     
         13 . A battery protection circuit comprising:
 a first semiconductor device that is the semiconductor device according to  claim 1 ;   a second semiconductor device that is the semiconductor device according to  claim 1 , the N vertical MOS transistors of which total three;   N−1 battery cells connected in a series connection;   a first terminal connected to the one or more source pads of a first terminal-connected vertical MOS transistor which is a single vertical MOS transistor among the N vertical MOS transistors included in the first semiconductor device, and to the one or more source pads of a second terminal-connected vertical MOS transistor which is a single vertical MOS transistor among the three vertical MOS transistors included in the second semiconductor device;   a second terminal connected to negative electrodes of the N−1 battery cells; and   a third terminal connected to a positive electrode of a battery cell, among the N−1 battery cells, located at a positive electrode end of the series connection, wherein   each positive electrode of the N−1 battery cells is connected to the one or more source pads of a different one of N−1 vertical MOS transistors among the N vertical MOS transistors included in the first semiconductor device excluding the first terminal-connected vertical MOS transistor,   among the N−1 battery cells, a positive electrode of a first battery cell located at a negative electrode end of the series connection is connected to the one or more source pads of one of two vertical MOS transistors among the three vertical MOS transistors included the second semiconductor device excluding the second terminal-connected vertical MOS transistor, and a negative electrode of a second battery cell located next to the first battery cell in the series connection is connected to the one or more source pads of an other of the two vertical MOS transistors among the three vertical MOS transistors included the second semiconductor device excluding the second terminal-connected vertical MOS transistor, and   the first battery cell and the second battery cell are connected in series via the second semiconductor device.   
     
     
         14 . A battery protection circuit comprising:
 a first semiconductor device that is the semiconductor device according to  claim 1 ;   a second semiconductor device that is the semiconductor device according to  claim 1 , the N vertical MOS transistors of which total three;   N battery cells connected in a series connection;   a first terminal connected to the one or more source pads of a first terminal-connected vertical MOS transistor which is a single vertical MOS transistor among the N vertical MOS transistors included in the first semiconductor device, and to the one or more source pads of a second terminal-connected vertical MOS transistor which is a single vertical MOS transistor among the three vertical MOS transistors included in the second semiconductor device;   a second terminal connected to negative electrodes of the N battery cells; and   a third terminal connected to a positive electrode of a battery cell, among the N battery cells, located at a positive electrode end of the series connection, wherein   each positive electrode of N−1 battery cells among the N battery cells excluding a first battery cell located at a negative electrode end of the series connection is connected to the one or more source pads of a different one of N−1 vertical MOS transistors among the N vertical MOS transistors included in the first semiconductor device excluding the first terminal-connected vertical MOS transistor,   among the N battery cells, a positive electrode of the first battery cell located at the negative electrode end of the series connection is connected to the one or more source pads of one of two vertical MOS transistors among the three vertical MOS transistors included the second semiconductor device excluding the second terminal-connected vertical MOS transistor, and a negative electrode of a second battery cell, among the N battery cells, located next to the first battery cell in the series connection is connected to the one or more source pads of an other of the two vertical MOS transistors among the three vertical MOS transistors included the second semiconductor device excluding the second terminal-connected vertical MOS transistor, and   the first battery cell and the second battery cell are connected in series via the second semiconductor device.   
     
     
         15 . A battery protection circuit comprising:
 a first semiconductor device that is the semiconductor device according to  claim 4 , the N vertical MOS transistors of which total three, the at least one specific vertical MOS transistor of which totals one;   a second semiconductor device that is the semiconductor device according to  claim 4 , the N vertical MOS transistors of which total three, the at least one specific vertical MOS transistor of which totals one;   a first terminal connected to the single source pad of the one specific vertical MOS transistor included in the first semiconductor device;   a second terminal connected to the one or more source pads of one of two vertical MOS transistors among the three vertical MOS transistors included in the first semiconductor device excluding the one specific vertical MOS transistor;   a third terminal connected to the one or more source pads of an other of the two vertical MOS transistors among the three vertical MOS transistors included in the first semiconductor device excluding the one specific vertical MOS transistor;   a fourth terminal connected to the single source pad of the one specific vertical MOS transistor included in the second semiconductor device;   a fifth terminal connected to the one or more source pads of one of two vertical MOS transistors among the three vertical MOS transistors included in the second semiconductor device excluding the one specific vertical MOS transistor; and   a sixth terminal connected to the one or more source pads of an other of the two vertical MOS transistors among the three vertical MOS transistors included in the second semiconductor device excluding the one specific vertical MOS transistor, wherein   the third terminal is for connecting to one or more positive electrodes of one or more battery cells,   the sixth terminal is for connecting to one or more negative electrodes of the one or more battery cells,   the first terminal, the second terminal, the fourth terminal, and the fifth terminal are for connecting to a power management circuit, and   through the second terminal and the fifth terminal, the power management circuit applies charging current to the one or more battery cells when charging, and receives discharging current from the one or more battery cells when discharging.   
     
     
         16 . A battery protection circuit comprising:
 the semiconductor device according to  claim 4 , the N vertical MOS transistors of which total three, the at least one specific vertical MOS transistor of which totals one;   a first terminal connected to the single source pad of the one specific vertical MOS transistor included in the semiconductor device and to the one or more source pads of one of two vertical MOS transistors among the three vertical MOS transistors included in the semiconductor device excluding the one specific vertical MOS transistor;   a second terminal connected to the one or more source pads of an other of the two vertical MOS transistors among the three vertical MOS transistors included in the semiconductor device excluding the one specific vertical MOS transistor;   a third terminal; and   a fourth terminal, wherein   the first terminal is for connecting to one or more positive electrodes of one or more battery cells,   the third terminal is for connecting to one or more negative electrodes of the one or more battery cells,   the second terminal and the fourth terminal are for connecting to a power management circuit, and   through the second terminal and the fourth terminal, the power management circuit applies charging current to the one or more battery cells when charging, and receives discharging current from the one or more battery cells when discharging.   
     
     
         17 . A battery protection circuit comprising:
 a first semiconductor device that is the semiconductor device according to  claim 1 , the N vertical MOS transistors of which total X+Y, where X is an integer greater than or equal to one and Y is an integer greater than or equal to two;   a second semiconductor device that is the semiconductor device according to  claim 1 , the N vertical MOS transistors of which total 1+Y;   X first terminals each connected to the one or more source pads of a different one of X vertical MOS transistors among the X+Y vertical MOS transistors included in the first semiconductor device;   Y second terminals each connected to the one or more source pads of a different one of Y vertical MOS transistors among the X+Y vertical MOS transistors included in the first semiconductor device excluding the X vertical MOS transistors;   a third terminal connected to the one or more source pads of a single vertical MOS transistor among the 1+Y vertical MOS transistors included in the second semiconductor device; and   Y fourth terminals each connected to the one or more source pads of a different one of Y vertical MOS transistors among the 1+Y vertical MOS transistors included in the second semiconductor device excluding the single vertical MOS transistor, wherein   the X first terminals are for connecting to respective positive electrodes of X battery cells,   the third terminal is for connecting to one or more negative electrodes of the X battery cells,   the Y second terminals and the Y fourth terminals are for connecting to respective Y power management circuits, and   through one of the Y second terminals and one of the Y fourth terminals, each of the Y power management circuits applies charging current to at least one battery cell among the X battery cells when charging, and receives discharging current from the at least one battery cell among the X battery cells when discharging.   
     
     
         18 . A power management circuit comprising:
 the semiconductor device according to  claim 1 , the N vertical MOS transistors of which total X+Y, where X is an integer greater than or equal to one and Y is an integer greater than or equal to two;   X terminals each connected to the one or more source pads of a different one of X vertical MOS transistors among the X+Y vertical MOS transistors included in the semiconductor device; and   Y circuits each connected to the one or more source pads of a different one of Y vertical MOS transistors among the X+Y vertical MOS transistors included in the semiconductor device excluding the X vertical MOS transistors, wherein   the X terminals are for connecting to respective X external circuits, and   each of the Y circuits has a separate power supply.   
     
     
         19 . A semiconductor device of chip-size package type that is face-down mountable, the semiconductor device comprising:
 a semiconductor layer; and   N vertical transistors in the semiconductor layer, where N is an integer greater than or equal to three, wherein   each of the N vertical transistors includes, on an upper surface of the semiconductor layer, a control pad electrically connected to a control electrode that controls conduction of the vertical transistor and one or more external connection pads electrically connected to an external connection electrode through which the vertical transistor receives current from outside or outputs current outside,   the semiconductor layer includes a semiconductor substrate,   the semiconductor substrate includes one main surface on which the N vertical transistors are formed and an other main surface facing away from the one main surface, and the semiconductor device further comprises a common electrode common to the N vertical transistors on the other main surface side of the semiconductor substrate,   for each of the N vertical transistors, a surface area of the vertical transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical transistor, and   for each of the N vertical transistors, the surface area of the vertical transistor in a plan view of the semiconductor layer is proportional to a square of the maximum specified current of the vertical transistor.   
     
     
         20 . The semiconductor device according to  claim 19 , wherein
 for each of the N vertical transistors, a conduction resistance when the maximum specified current flows is inversely proportional to the square of the maximum specified current of the vertical transistor.   
     
     
         21 . The semiconductor device according to  claim 19 , further comprising:
 a common terminal that is on an upper surface side of the semiconductor layer and electrically connected to the common electrode.   
     
     
         22 . The semiconductor device according to  claim 21 , wherein
 each of the one or more external connection pads included in each of the N vertical transistors is an external output terminal through which current from the N vertical transistors is output outside the N vertical transistors, and   the common terminal is an external input terminal through which outside current is input into the N vertical transistors.