Hybrid polysilicon heterojunction back contact cell
Abstract
A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A solar cell, comprising:
a silicon substrate, wherein the silicon substrate has a first surface opposite a second surface; a thin oxide layer disposed on a first portion of the first surface of the silicon substrate; a thin dielectric layer disposed on a second portion of the first surface of the silicon substrate, wherein a portion of the thin oxide layer is in contact with and disposed over the thin dielectric layer; a first wide band gap doped semiconductor of a first conductivity type disposed on the thin oxide layer; a crystalline doped silicon of a second conductivity type disposed on the thin dielectric layer, wherein a portion of the first wide band gap doped semiconductor is disposed over the crystalline doped silicon and the thin dielectric layer; a doping material disposed on the crystalline doped silicon; a first contact disposed directly on the first wide band gap doped semiconductor; and a second contact disposed on the crystalline doped silicon, wherein the second contact is disposed over and through the doping material, first wide band gap doped semiconductor and the thin oxide layer.
2 . The solar cell of claim 1 , wherein the silicon substrate is an N-type bulk silicon.
3 . The solar cell of claim 1 , further comprising:
a second wide band gap doped semiconductor disposed proximate to the second surface of the silicon substrate.
4 . The solar cell of claim 3 , further comprising:
an anti-reflective coating disposed on the second wide band gap doped semiconductor.
5 . The solar cell of claim 1 , wherein the first wide band gap doped semiconductor has a band gap greater than 1.05 electron-Volts.
6 . The solar cell of claim 1 , wherein the first wide band gap doped semiconductor has a resistivity of greater than 10 ohm-cm.
7 . The solar cell of claim 1 , wherein the second surface of the silicon substrate comprises a texturized surface, and wherein the second wide band gap doped semiconductor is conformal to the texturized surface.
8 . The solar cell of claim 1 , wherein the first portion of the first surface of the silicon substrate comprises a texturized surface.
9 . The solar cell of claim 8 , wherein a portion of the first wide band gap doped semiconductor and a portion of the thin oxide layer are conformal to the texturized surface of the first surface.
10 . The solar cell of claim 1 , wherein the doping material comprises a positive-type doping material.
11 . A method of fabricating a solar cell, the method comprising:
forming a thin oxide layer on a first portion of a first surface of a silicon substrate, the first surface opposite a second surface; forming a thin dielectric layer on a second portion of the first surface of the silicon substrate, wherein a portion of the thin oxide layer is in contact with and over the thin dielectric layer; forming a first wide band gap doped semiconductor of a first conductivity type on the thin oxide layer; forming a crystalline doped silicon of a second conductivity type on the thin dielectric layer, wherein a portion of the first wide band gap doped semiconductor is over the crystalline doped silicon and the thin dielectric layer; forming a doping material on the crystalline doped silicon; forming a first contact directly on the first wide band gap doped semiconductor; and forming a second contact on the crystalline doped silicon, wherein the second contact is over and through the doping material, first wide band gap doped semiconductor and the thin oxide layer.
12 . The method of claim 11 , wherein the silicon substrate is an N-type bulk silicon.
13 . The method of claim 11 , further comprising:
forming a second wide band gap doped semiconductor proximate to the second surface of the silicon substrate.
14 . The method of claim 13 , further comprising:
forming an anti-reflective coating on the second wide band gap doped semiconductor.
15 . The method of claim 11 , wherein the first wide band gap doped semiconductor has a band gap greater than 1.05 electron-Volts.
16 . The method of claim 11 , wherein the first wide band gap doped semiconductor has a resistivity of greater than 10 ohm-cm.
17 . The method of claim 11 , wherein the second surface of the silicon substrate comprises a texturized surface, and wherein the second wide band gap doped semiconductor is conformal to the texturized surface.
18 . The method of claim 11 , wherein the first portion of the first surface of the silicon substrate comprises a texturized surface.
19 . The method of claim 18 , wherein a portion of the first wide band gap doped semiconductor and a portion of the thin oxide layer are conformal to the texturized surface of the first surface.
20 . The method of claim 11 , wherein the doping material comprises a positive-type doping material.Join the waitlist — get patent alerts
Track US2023238471A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.