Optimizing power usage by factoring processor architectural events to pmu

Abstract

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

1 .- 39 . (canceled) 
     
     
         40 . A processor comprising:
 logic circuitry configured to detect whether at least one of a plurality of architectural events has occurred within a processor core;   a plurality of counters, at least one of the plurality of counters being configured to count a number of occurrences of the at least one of the plurality of architectural events;   a system interconnect that supports power scaling; and   a power unit configured to cause a power sequence in response to occurrence of the at least one of the plurality of architectural events, wherein   the power unit is configured to modify a power state of the processor core and a power state of the system interconnect based on one or more values of the at least one of the plurality of counters.   
     
     
         41 . The processor of  claim 40 , wherein each of the plurality of counters is configured to count a number of occurrences of a respective one of the plurality of architectural events. 
     
     
         42 . The processor of  claim 40 , wherein the power sequence comprises powering up the processor core and the system interconnect if reserve power is available, remaining idle if no reserve power is available, and powering down the processor core and the system interconnect. 
     
     
         43 . The processor of  claim 40 , wherein the power unit is further configured to increase one or both of a frequency of the processor core or a bandwidth of the system interconnect if each of the plurality of counters is below a corresponding count threshold. 
     
     
         44 . The processor of  claim 40 , wherein the power unit is further configured to decrease one or both of a frequency of the processor core or a bandwidth of the system interconnect if one of the plurality of counters corresponding to cache misses is greater than a corresponding count threshold. 
     
     
         45 . The processor of  claim 40 , wherein the power unit is further configured to scale the power state of the processor core and the power state of the system interconnect using a same mechanism. 
     
     
         46 . The processor of  claim 40 , wherein the system interconnect connects the processor to one or more of a shared cache, a bus control logic, or an on-die memory control. 
     
     
         47 . A method comprising:
 generating a signal in a processor, the signal indicating an occurrence of at least one of a plurality of architectural events within a processor core;   counting, by at least one of a plurality of counters, a number of occurrences of the at least one of the plurality of architectural events;   causing, at a power unit, a power sequence based on the occurrence of the at least one of the plurality of architectural events; and   modifying, by the power unit, a power state of the processor core and a power state of a system interconnect based on one or more values of the at least one of the plurality of counters, wherein   the system interconnect supports power scaling.   
     
     
         48 . The method of  claim 47 , wherein each of the plurality of counters counts a number of occurrences of a respective one of the plurality of architectural events. 
     
     
         49 . The method of  claim 47 , wherein the power sequence comprises powering up the processor core and the system interconnect if reserve power is available, remaining idle if no reserve power is available, and powering down the processor core and the system interconnect. 
     
     
         50 . The method of  claim 47 , wherein in the power sequence, the power unit increases one or both of a frequency of the processor core or a bandwidth of the system interconnect if each of the plurality of counters is below a corresponding count threshold. 
     
     
         51 . The method of  claim 47 , wherein in the power sequence, the power unit decreases one or both of a frequency of the processor core or a bandwidth of the system interconnect if one of the plurality of counters corresponding to cache misses is greater than a corresponding count threshold. 
     
     
         52 . The method of  claim 47 , wherein in the power sequence, the power unit scales the power state of the processor core and the power state of the system interconnect using a same mechanism. 
     
     
         53 . The method of  claim 47 , wherein the system interconnect connects the processor to one or more of a shared cache, a bus control logic, or an on-die memory control. 
     
     
         54 . A system comprising:
 a memory configured to store architectural event data corresponding to a plurality of architectural events;   logic circuitry configured to detect whether at least one of the plurality of architectural events has occurred within a processor core;   a plurality of counters, at least one of the plurality of counters being configured to count a number of occurrences of the at least one of the plurality of architectural events;   a system interconnect that supports power scaling; and   a power unit configured to cause a power sequence in response to occurrence of the at least one of the plurality of architectural events, wherein   the power unit is configured to modify a power state of the processor core and a power state of the system interconnect based on one or more values of the at least one of the plurality of counters.   
     
     
         55 . The system of  claim 54 , wherein each of the plurality of counters is configured to count a number of occurrences of a respective one of the plurality of architectural events. 
     
     
         56 . The system of  claim 54 , wherein the power sequence comprises powering up the processor core and the system interconnect if reserve power is available, remaining idle if no reserve power is available, and powering down the processor core and the system interconnect. 
     
     
         57 . The system of  claim 54 , wherein the power unit is further configured to increase one or both of a frequency of the processor core or a bandwidth of the system interconnect if each of the plurality of counters is below a corresponding count threshold. 
     
     
         58 . The system of  claim 54 , wherein the power unit is further configured to decrease one or both of a frequency of the processor core or a bandwidth of the system interconnect if one of the plurality of counters corresponding to cache misses is greater than a corresponding count threshold. 
     
     
         59 . The system of  claim 54 , wherein the power unit is further configured to scale the power state of the processor core and the power state of the system interconnect using a same mechanism. 
     
     
         60 . The processor of  claim 54 , wherein the system interconnect connects the processor to one or more of a shared cache, a bus control logic, or an on-die memory control.