Expanding a role of a dedicated pin

Abstract

Disclosed embodiments include a processing system. The processing system includes an internal element including a slave controller. The processing system also includes a master controller configured for communication with the internal element. the internal element is configured to activate an error indication via an alert channel to the master controller responsive to an error signal from the slave controller. Further, the internal element is configured to activate a data ready indication via the alert channel responsive to a data ready signal from the slave controller.

1 - 26 . (canceled) 
     
     
         27 . A processing system comprising:
 an internal element including a slave controller, and   a master controller configured for communication with the internal element,   wherein
 responsive to an error signal from the slave controller, the internal element is configured to activate an error indication via an alert channel to the master controller, and 
 responsive to a data ready signal from the slave controller, the internal element is configured to activate a data ready indication via the alert channel. 
   
     
     
         28 . The processing system of  claim 27 , wherein the master controller further includes a memory controller configured to communicate with the internal element. 
     
     
         29 . The processing system of  claim 27  wherein the error signal indicates a computer memory access error. 
     
     
         30 . The processing system of  claim 27  wherein the data ready signal indicates the internal element has data ready to be sent to the master controller. 
     
     
         31 . The processing system of  claim 27 , wherein the master controller is configured:
 in response to receiving the error indication via the alert channel, to cause at least one first action to be taken, and   in response to receiving the data ready indication via the alert channel, to cause at least one second action to be taken.   
     
     
         32 . The processing system of  claim 31  wherein the at least one first action includes terminating access to memory. 
     
     
         33 . The processing system of  claim 31  wherein the at least one second action includes initiating access to memory. 
     
     
         34 . The system of  claim 27  wherein the master controller is configured that based on receiving the data ready indication to initiate reading data via the slave controller from a computer memory associated with the internal element. 
     
     
         35 . The system of  claim 34  wherein reading data is via a data link layer communication channel. 
     
     
         36 . The processing system of  claim 27 , wherein the internal element is a memory processing module including one or more processor subunits and one or more memory banks formed on a common substrate. 
     
     
         37 . The processing system of  claim 27  wherein the memory controller is a DDR4 controller. 
     
     
         38 . The processing system of  claim 27  wherein the error signal is a DDR4 ALERT_N signal. 
     
     
         39 . The processing system of  claim 27  wherein the internal element further includes an output buffer, and when the output buffer has data to send, the internal element activates the data ready indication.