Fast, energy efficient cmos 2p1r1w register file array using harvested data

Abstract

A transistor memory device includes storage elements storing a capacitance including (1) a capacitance at a source of PFETs, (2) a capacitance at each storage element connected to a storage node and (3) a capacitance at a gate input of inverter transistors from the plurality of transistor storage elements. Each storage element configured to perform (i) a read data access (ii) a write data access, to increase static noise margin. The transistor memory device further includes a harvest node coupled to a ground and that is configured to store a harvested charge transferred from a selected bitline to increase an output voltage at the harvest node. The transistor memory device further includes a capacitor divider configured to maintain a voltage swing on a bitline. The transistor memory device further includes a harvest circuit configured to, in response to the read data access, decouple the harvest node and invert a voltage.

1 . A Register File memory device comprising:
 a plurality of conventional 8 transistor 2 port storage elements each with 1 read port and 1 write port and each with a decoupled read stack of a pair of NFETs with the gate input of one driven by a Read word line and the gate input of the other in the pair driven by a cell storage node.   a harvest terminal that replaces the reference ground potential terminal of the decoupled read stack of FETs in a conventional Register File storage element.   a harvest circuit coupled to the harvest terminal of a plurality of storage elements whose Read ports are coupled along a common bitline with the harvest circuit responsive to a read access by self-disabling the development of signal on the bitline, eliminating the uncertainty of signal voltage development on the bitline due to the statistical variation of read current read stack and at least doubling the rate at which data sensed in the selected storage element is resolved.   
     
     
         2 . An apparatus, comprising:
 a plurality of transistor storage elements, a transistor storage element from the plurality of transistor storage elements including a read port and a write port, the transistor storage element electrically from the plurality of transistor storage elements coupled to a first n-channel field effect transistor (NFET) and a second NFET, the second NFET including a gate terminal configured to be driven by a bitcell including a read word line, the first NFET including a source terminal and a gate terminal such that the gate terminal of the first NFET is configured to be driven by a cell storage node for the read port from the transistor storage element;   a bitline electrically coupled to the read port of the transistor storage element from the plurality of transistor storage elements and configured to be precharged;   a harvesting node electrically coupled to the source terminal of the first NFET and configured to harvest, at the harvesting node, voltage that was precharged at the bitline in response to a read access action and an activation of the cell storage node;   a harvest inverter including a reference ground potential terminal configured to be replaced with the harvesting node, the harvest inverter including a gate terminal configured to be electrically coupled to the read port of the transistor storage element from the plurality of transistor storage elements; and   a harvesting grid electrically coupled to the harvesting node, the harvesting grid configured to self-disable a signal development on the bitline to eliminate an uncertainty of the signal development on the bitline when an electric potential of harvested data on the harvesting node matches a voltage at the bitline from the signal development.   
     
     
         3 . The apparatus of  claim 2 , wherein the harvesting node configured to discharge a voltage to the reference ground potential before the read access through the first NFET having an active high pulse at the gate terminal of the first NFET enabling discharge of the voltage. 
     
     
         4 . The apparatus of  claim 3 , wherein the gate terminal of the harvest inverter is electrically coupled to the bitline, the harvest inverter including an output terminal configured to be triggered by (1) a decreasing electric potential difference between the bitline that is precharged and the harvesting node during the read access when the cell storage node is active and electrically coupled to the first NFET or the second NFET or (2) a voltage substantially equal to a voltage at a power supply terminal that is electrically coupled to the transistor storage element, the output terminal configured to be triggered by movement of electric charge from the gate terminal of the harvest inverter to the harvesting node. 
     
     
         5 . The apparatus of  claim 2 , wherein:
 the apparatus is configured to perform a global sensing scheme such that the gate terminal of the harvest inverter is electrically coupled to a global bitline that is electrically coupled to a drain terminal of the first NFET and a drain terminal of the second NFET, the gate terminal of the first NFET and the gate terminal of the second NFET being driven by the bitline,   the reference ground potential terminal of the harvest inverter configured to be replaced with a global harvest terminal that is electrically coupled to the source terminal of the first NFET, the global harvest terminal configured to harvest charge from the global bitline that is precharged as the first NFET is triggered by a rising output at an output terminal of the harvest inverter.   
     
     
         6 . The apparatus of  claim 2 , wherein the transistor storage element from the plurality of transistor storage elements is configured to be decoupled from the first NFET and the second NFET to enable a higher read performance without compromising read stability margins. 
     
     
         7 . The apparatus of  claim 2 , wherein a discharge of voltage at the bitline is configured to stop in response to a rising voltage at the harvesting node asymptotically approaching a noise voltage at the gate terminal of the first NFET. 
     
     
         8 . The apparatus of  claim 2 , wherein a voltage signal developed at the bitline is determined by a capacitive divide electrically coupled between the bitline and the harvesting node. 
     
     
         9 . The apparatus of  claim 2 , wherein harvested charge stored at the harvesting node is configured to self-disable a flow of read current as the harvested charge at the harvesting node approaches a noise voltage at the bit storage node. 
     
     
         10 . The apparatus of  claim 2 , wherein the signal development on the bitline is configured to self-disable as the electric potential of the harvested data at the harvesting node rises to equalize a dropping voltage of the bitline. 
     
     
         11 . The apparatus of  claim 2 , wherein the harvesting grid is configured to self-disable when the first NFET and the second NFET have insufficient gate overdrive. 
     
     
         12 . The apparatus of  claim 2 , wherein a capacitance of the harvesting node is fixed and cannot be changed to charge the harvesting node to a different voltage. 
     
     
         13 . The apparatus of  claim 2 , wherein a voltage at the harvesting node is configured to increase while the bitline loses charge, to increase a signal development rate for the voltage signal. 
     
     
         14 . The apparatus of  claim 2 , wherein a change in voltage, in response to a charge being transferred from the bitline to the harvesting node when the bitline including the read word line is selected, is the same as when a bitline including a write word line is selected. 
     
     
         15 . The apparatus of  claim 2 , further comprising an inverter electrically coupled to the bitline and the harvesting node, the inverter including an input terminal and an output terminal, the output terminal configured to perform a low-to-high transition in response to a voltage at the bitline and a voltage at the harvesting node being within a voltage threshold. 
     
     
         16 . The apparatus of  claim 2 , wherein increasing a voltage at the harvesting node occurs at a same time as and at a same rate of a voltage at the bitline is lowered.