Circuits & methods to harvest energy from transient data

Abstract

An apparatus includes a circuit having an inverter including a power supply, an input terminal and an output terminal, and a harvest terminal electrically coupled to the output terminal. The circuit electrically couples the output terminal and the power supply, such that (1) a harvested charge is transferred from an output voltage at the output terminal to the harvest terminal in response to a high-to-low transition at the circuit and (2) a low-to-high transition at the circuit is driven using at least the harvested charge at the harvest terminal in response to the high-to-low transition.

What is claimed is: 
     
         1 . An inverter partially powered by harvested charge comprising of
 N and P channel FETs with their drain terminals shorted together at the output terminal of the inverter. The source terminals of the N and P channel FETs are connected to the reference Ground and Power supply rails respectively.   a second N channel FET whose source and drain terminals couple the output terminal of the inverter with a grid/node whose capacitance holds harvested charge at a voltage larger than the reference ground potential.   an input terminal and an output terminal of the inverter whose electric potentials makes full-swing transitions between the power rail voltage and the reference ground rail voltage. The input terminal of the inverter connected directly to the gate input, terminal of the first N channel FET.   a small HVT keeper P channel FET whose gate input terminal is driven by the input terminal of the inverter and whose source and drain terminals are connected to the power rail at voltage VDD and the output terminal of the inverter   a 2-input NOR gate with its inputs driven by the input and output terminals of the inverter. The 2-input NOR gate output drives the gate input terminal of the second N channel FET and the input terminal of a delay element whose inverted output drives the p channel FET of the inverter   
     
     
         2 . The device as recited in  claim 1  wherein the second N channel FET is enabled to move charge from the grid/node holding harvested charge to the output terminal of the inverter following a 1→0 logic transition at the input terminal of the inverter with this charge transfer self-disabled by a rising inverter output voltage that resets the output of the NOR gate to the reference ground potential as the inverter output voltage approaches the logic threshold voltage of the NOR gate. 
     
     
         3 . The device as recited in  claims 1 ,  2  wherein the rising inverter output voltage is reinforced by the P channel FET of the inverter when the delayed, leading-edge 1→0 transition at the gate input terminal of the P channel FET completes the 0→1 transition at the output of the inverter by transferring charge from the power rail to the output of the inverter. 
     
     
         4 . The NOR gate is designed to have a logic threshold such that the voltage V2 at which harvested charge is held is comparable to the logic threshold of the NOR gate. The delay element is designed to have a delay that is comparable to the time it takes for the output to rise from voltage VSS=0V to a voltage comparable to the logic threshold of the NOR.