Core group memory processing with group b-float encoding

Abstract

A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of memory regions. The plurality of memory regions can be organized in a plurality of memory blocks. The plurality of memory regions can be configured to store integer, B-float, and/or Group B-float encode data. The plurality of processing regions can be interleaved between the plurality of processing regions of the first memory. The plurality of processing regions can be organized in a plurality of core groups include a plurality of compute cores. The compute groups in the processing regions can be coupled to a plurality of adjacent memory blocks in the adjacent memory regions. The second memory can be coupled to the plurality of processing regions.

What is claimed is: 
     
         1 . A memory processing unit (MPU) comprising:
 a first memory including a plurality of memory regions, wherein one or more of the plurality of memory regions are configured in a corresponding pluralities of memory blocks, wherein the memory blocks are configured to store Brian Floating Point (B-float) encoded data; and   a plurality of processing regions interleaved between the plurality of regions of the first memory, wherein the processing regions include a plurality of core groups, wherein the core groups include one or more compute cores.   
     
     
         2 . The MPU of  claim 1 , wherein the memory blocks are further configured to store Group B-float encoded data. 
     
     
         3 . The MPU of  claim 2 , wherein the Group B-float encoded data comprises Group B-float encoded feature map pixels values. 
     
     
         4 . The MPU of  claim 2 , wherein the plurality of memory blocks of each of the plurality of regions of the first memory are arranged in a plurality of columns and rows. 
     
     
         5 . The MPU of  claim 4 , wherein a plurality of bases and an instance of a given exponent for a corresponding group of channels of the Group B-float encoded data are store in a corresponding row of memory blocks of a corresponding region of the first memory. 
     
     
         6 . The MPU of  claim 5 , wherein the exponent for corresponding groups of channels of the Group B-float encoded data are dynamic. 
     
     
         7 . The MPU of  claim 1 , wherein one or more of the plurality of core groups of a respective one of the plurality of processing regions are coupled between adjacent ones of the plurality of memory regions of the first memory, and between adjacent core groups of the respective one of the plurality of processing regions. 
     
     
         8 . The MPU of  claim 1 , wherein the plurality of core groups of respective ones of the plurality of processing regions are coupled between adjacent ones of the plurality of memory regions of the first memory. 
     
     
         9 . The MPU of  claim 1 , wherein compute cores of respective ones of the core groups are configured in one or more compute clusters, wherein compute cores in a given compute cluster are configured to compute a given compute function. 
     
     
         10 . The MPU of  claim 9 , wherein one or more compute groups include one or more memory M-cores and one or more arithmetic A-Cores. 
     
     
         11 . A memory processing unit (MPU) comprising:
 a first memory including a plurality of memory regions, wherein the plurality of memory regions are configured in corresponding pluralities of memory blocks, and wherein the memory blocks are configured to store Group B-float encoded feature map pixels; and   a plurality of processing regions columnal interleaved between the plurality of regions of the first memory, wherein the plurality of core groups of respective ones of the plurality of processing regions are coupled between adjacent ones of the plurality of memory regions of the first memory and between adjacent core groups within the respective processing region.   
     
     
         12 . The MPU of  claim 11 , wherein the plurality of memory blocks of each of the plurality of regions of the first memory are arranged in a plurality of columns and rows. 
     
     
         13 . The MPU of  claim 11 , wherein a plurality of bases and an instance of a give exponent for a corresponding group of channels of the Group B-float encoded data are stored in a corresponding row of memory blocks of a corresponding region of the first memory 
     
     
         14 . The MPU of  claim 10 , further comprising one or more memory regions of a second memory coupled to the plurality of processing regions. 
     
     
         15 . The MPU of  claim 14 , wherein the second memory is configured to store weight values. 
     
     
         16 . The MPU of  claim 14 , wherein respect ones of the second memory regions are coupled to respective ones of the plurality of processing regions. 
     
     
         17 . The MPU of  claim 14 , further wherein the compute cores in corresponding core groups of the plurality of processing regions are:
 configurable for core-to-core dataflow between adjacent compute groups in respective ones of the plurality of processing regions through one or more corresponding memory blocks of a corresponding memory region;   configurable for memory-to-core dataflow from respective ones of memory blocks of the plurality of regions of the first memory to one or more cores within adjacent ones of core groups of the plurality of processing regions;   configurable for core-to-memory dataflow from one or more cores within ones of the plurality of core groups of the plurality of processing regions to adjacent ones of the memory blocks of the plurality of regions of the first memory; and   configurable for memory-to-core dataflow from the second memory region to one or more core groups of corresponding ones of the plurality of processing regions.   
     
     
         18 . The MPU of  claim 11 , wherein:
 the first memory comprises a static volatile memory; and   the second memory comprises a non-volatile memory.   
     
     
         19 . A memory processing method comprising:
 configuring a first memory to store Group B-float encoded data, wherein the first memory includes a plurality of regions;   configuring data flow between compute cores of one or more of a plurality of processing regions and corresponding adjacent ones of the plurality of regions of the first memory;   configuring data flow between a second memory and the compute cores of the one or more of the plurality of processing regions;   configuring data flow between compute cores within respective ones of the one or more of the plurality of processing regions;   configuring one or more sets of compute cores of one or more of the plurality of processing regions to perform respective compute functions of a neural network model;   loading weights for the neural network model into the second memory;   loading activation data for the neural network model into one or more of the plurality of regions of the first memory;   synchronizing data movement between one or more compute cores producing given data and one or more other compute cores consuming the given data based on the neural network model.   
     
     
         20 . The memory processing method according to  claim 19 , wherein the plurality of regions of the first memory each include a plurality of memory block arranged in a plurality of columns and rows. 
     
     
         21 . The memory processing method according to  claim 20 , further comprising configuring the first memory to store a plurality of bases and an instance of a given exponent for a corresponding group of channels of the Group B-float encoded data in a corresponding row of memory blocks of a corresponding region of the first memory. 
     
     
         22 . The memory processing method according to  claim 21 , wherein the exponent for corresponding groups of channels of the Group B-float encoded data are dynamic.