Management of non-volatile memory arrays

Abstract

The system may include a digital-to-analog converter configured to convert a digital signal to an analog signal. The system may include sample/hold circuits configured to receive and store the analog signal. The system may include an address controller configured to regulate which sample/hold circuits propagate the analog signal. The sample/hold circuits may be configured to feed the analog signal to devices of a memory array. The system may include an output circuit configured to program the devices by comparing currents of the devices to a target current. In response to one or more of the currents of the devices being within a threshold range, the output circuit may discontinue programming the corresponding devices. In response to one or more of the currents of the devices not being within the threshold range, the output circuit may continue programming the corresponding devices.

What is claimed is: 
     
         1 . A memory programming system comprising:
 a memory array comprising a plurality of devices; and   an output circuit comprising:
 a current-to-voltage converter circuit comprising:
 an operational amplifier comprising an input node selectively connected to the memory array and an output node, the operational amplifier configured to convert an input current received at the input node to an operational amplifier voltage at the output node, wherein the input node is configured to receive a target current or a memory array current via a switch; 
 a sample-and-hold circuit comprising an input node connected to the output node of the operational amplifier and an output node connected to the input node of a comparator circuit, the sample-and-hold circuit configured to sample and hold the operational amplifier voltage to generate a sample-and-hold voltage; and 
 the comparator circuit comprising: 
 a first input node selectively connected to the output node of the sample-and-hold circuit; 
 a second input node selectively connected to the output node of the operational amplifier; and 
 an output node, the comparator circuit configured to generate a positive or high voltage when the sample-and-hold voltage is greater than the operational amplifier voltage and to generate a negative or low voltage when the sample-and-hold voltage is less than the operational amplifier voltage, 
 
   wherein the output circuit is configured to first connect the input node of the operational amplifier to the memory array and the output node of the operational amplifier to the sample-and-hold circuit to convert and store the voltage corresponding to the memory array current in the sample-and-hold circuit and disconnect the input node of the operational amplifier and the output nodes from the memory array and the sample-and-hold circuit and connect the input node of the operational amplifier to the target current and the output node of the operational amplifier to the second input node of the comparator circuit to compare the memory array current and the target current.   
     
     
         2 . The memory programming system of  claim 1 , wherein the output circuit further comprises a programming avoidance circuit connected to a subset of the plurality of devices to stop a programming current non-volatile state of the subset of the plurality of devices. 
     
     
         3 . The memory programming system of  claim 1 , wherein the comparator circuit further comprises a detector circuit connected to the output node of the comparator circuit and configured to convert an output voltage of the comparator circuit from an analog signal to a digital signal. 
     
     
         4 . The memory programming system of  claim 3 , wherein the detector circuit comprises a sign-change detector circuit. 
     
     
         5 . The memory programming system of  claim 1 , wherein the comparator circuit further comprises a flip flop circuit connected to the output node and configured to change a value of an output of the flip flop circuit to control programming of the devices within the memory array. 
     
     
         6 . The memory programming system of  claim 1 , wherein the current-to-voltage converter circuit further comprises a feedback component having a first end connected to the output node of the operational amplifier and a second end connected to the input node of the operational amplifier. 
     
     
         7 . A memory programming system comprising:
 a memory array comprising a plurality of devices; and   an output circuit comprising:
 a current-to-voltage converter circuit comprising:
 an operational amplifier comprising an input node connected to the memory array and an output node connected to a comparator circuit, the operational amplifier configured to convert an input current received at the input node to an operational amplifier voltage at the output node; 
 a sample-and-hold circuit comprising an input node receiving a target voltage and an output node connected to the input node of the comparator circuit, the sample-and-hold circuit configured to sample and hold the target voltage to generate a sample-and-hold voltage; and 
 the comparator circuit comprising: 
 a first input node connected to the output node of the sample-and-hold circuit; 
 a second input node connected to the output node of the operational amplifier; and 
 an output node, the comparator configured such that the output node includes a positive or high voltage when the sample-and-hold voltage is greater than the operational amplifier voltage and such that the output node includes a negative or low voltage when the sample-and-hold voltage is less than the operational amplifier voltage, 
 
   wherein the output circuit is configured to:
 convert a memory array current to a voltage; 
 compare the voltage to the sample-and-hold voltage; and 
 responsive to the voltage and the sample-and-hold voltage being within a threshold value, the comparator circuit is configured to switch a sign or a voltage and stop programming the plurality of devices within the memory array. 
   
     
     
         8 . The programming system of  claim 7 , wherein the output circuit further comprises a programming avoidance circuit connected to a subset of the plurality of devices to stop programming current non-volatile state of the subset of the plurality of devices. 
     
     
         9 . The programming system of  claim 7 , wherein the comparator circuit further comprises a detector circuit connected to the output node of the comparator circuit and configured to convert the output voltage of the comparator circuit from an analog signal to a digital signal. 
     
     
         10 . The programming system of  claim 9 , wherein the detector circuit comprises a sign-change detector circuit. 
     
     
         11 . The programming system of  claim 7 , wherein the comparator circuit further comprises a flip flop circuit connected to the output node and configured to change a value of an output of the flip flop circuit to control programming of the plurality of devices within the memory array. 
     
     
         12 . The programming system of  claim 7  wherein the current-to-voltage converter further comprises a feedback component comprising a first end connected to the output node of the operational amplifier and a second end connected to the input node of the operational amplifier. 
     
     
         13 . A parallel current reading system for memory arrays comprising:
 a memory array comprising a plurality of devices; and   an output circuit comprising:
 a binary counter configured to generate a binary counter signal; and 
 a plurality of digital-to-analog converters, each including an input node connected to an output of the binary counter and an output node connected to a comparator of a plurality of comparators, the plurality of digital-to-analog converters configured to receive the binary counter signal from the binary counter and convert the binary counter signal to a respective analog voltage or a current signal; and 
 the plurality of comparators, each including a first input connected to an output of the memory array and a second input connected to the output nodes of the plurality of digital to analog converters, the plurality of comparators configured such that the output nodes include a positive or high voltage when the signal received from memory array is greater than the signal received from the plurality of digital-to-analog converters and such that the output nodes include a negative or low voltage when the signal received from the memory array is less than the signal received from the plurality of digital-to-analog converters, 
 wherein the output circuit is configured to trigger the binary counter to generate the binary counter signal, the plurality of digital-to-analog converters receive the binary counter signal and convert the binary counter signal to an analog signal, the plurality of comparators receive the analog signal representing the binary counter signal and compare the analog signal with a signal received from the memory array, and responsive to the outputs of the plurality of comparators switching signs. 
   
     
     
         14 . The parallel current reading system of  claim 13 , wherein the plurality of comparators comprises current or voltage comparators. 
     
     
         15 . The parallel current reading system of  claim 13 , wherein the plurality of digital-to-analog converters generate a current or a voltage output. 
     
     
         16 . The parallel current reading system of  claim 13 , wherein the plurality of digital-to-analog converters comprises a single digital-to-analog converter that converts the binary counter signal and provides the analog signal to the plurality of comparators. 
     
     
         17 . The parallel current reading system of  claim 16 , wherein the single digital-to-analog converter converts the binary counter signal to an analog current signal, converts the analog current signal to a voltage, and provides the voltage to the plurality of the comparators. 
     
     
         18 . The parallel current reading system of  claim 16 , the output circuit further comprising a plurality of registers, each including an input bus connected to an output of the binary counter and an input trigger connected to the output nodes of the plurality of comparators. 
     
     
         19 . The parallel current reading system of  claim 18  wherein the plurality of comparators are configured to trigger the plurality of registers to latch a value of the binary counter. 
     
     
         20 . The parallel current reading system of  claim 13 , wherein the binary counter is configured to count from 0 to N or from N to 0 every time memory array currents of the memory array are measured.