Multi-thread graphics processing system

Abstract

A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

1 . A graphics processing system comprising:
 a sequencer logic configured to:
 receive a first command thread and a second command thread from a buffer, wherein the first command thread and the second command thread relate to application of textures; 
 perform interleaved execution of the first command thread and the second command thread; and 
   a pipeline, coupled to the sequencer logic, configured to provide vector analysis on the executed first command thread and the second command thread.   
     
     
         2 . The graphics processing system of  claim 1 , wherein the sequencer logic is an multiple arithmetic logic unit (ALU) system resource. 
     
     
         3 . The graphics processing system of  claim 1 , wherein the pipeline is an eight stage deep pipeline. 
     
     
         4 . The graphics processing system of  claim 1 , wherein the sequencer logic is further configured to select the first command thread or the second command thread by:
 analyzing a vertex reservation station and a pixel reservation station on which either the first command thread or the second command thread are stored; and   determining which of the first command thread or the second command thread is ready to execute.   
     
     
         5 . The graphics processing system of  claim 4 , wherein performing the interleaved execution of the first command thread and the second command thread is based on even and odd clock cycles. 
     
     
         6 . The graphics processing system of  claim 5 , wherein the sequencer logic is further configured to return the executed first command thread or the second command thread to the vertex reservation station or the pixel reservation station from which it originated. 
     
     
         7 . The graphics processing system of  claim 1 , wherein the first command thread or the second command thread are stored across two physical pieces of memory. 
     
     
         8 . The graphics processing system of  claim 7 , wherein a majority of bits of the first command thread or the second command thread are stored in a one read port device. 
     
     
         9 . The graphics processing system of  claim 7 , wherein bits of the first command thread or the second command thread required for thread arbitration are stored in a multi-ported structure. 
     
     
         10 . The graphics processing system of  claim 7 , wherein the two physical pieces of memory are physically separated. 
     
     
         11 . A method of operating a graphics processing system comprising:
 receiving, by a sequencer logic, a first command thread and a second command thread from a buffer, wherein the first command thread and the second command thread relate to application of textures;   performing, by the sequencer logic, interleaved execution of the first command thread and the second command thread; and   providing, by a pipeline coupled to the sequencer logic, vector analysis on the executed first command thread and the second command thread.   
     
     
         12 . The method of  claim 11 , wherein the sequencer logic is an multiple arithmetic logic unit (ALU) system resource. 
     
     
         13 . The method of  claim 11 , wherein the pipeline is an eight stage deep pipeline. 
     
     
         14 . The method of  claim 11 , further comprising selecting, by the sequencer logic, the first command thread or the second command thread by:
 analyzing a vertex reservation station and a pixel reservation station on which either the first command thread or the second command thread are stored; and   determining which of the first command thread or the second command thread is ready to execute.   
     
     
         15 . The method of  claim 14 , wherein performing the interleaved execution of the first command thread and the second command thread is based on even and odd clock cycles. 
     
     
         16 . The method of  claim 15 , further comprising returning, by the sequencer logic, the executed first command thread or the second command thread to the vertex reservation station or the pixel reservation station from which it originated. 
     
     
         17 . The method of  claim 11 , wherein the first command thread or the second command thread are stored across two physical pieces of memory. 
     
     
         18 . The method of  claim 17 , wherein a majority of bits of the first command thread or the second command thread are stored in a one read port device. 
     
     
         19 . The method of  claim 17 , wherein bits of the first command thread or the second command thread required for thread arbitration are stored in a multi-ported structure. 
     
     
         20 . The method of  claim 17 , wherein the two physical pieces of memory are physically separated.