Iii-nitride devices including a depleting layer

Abstract

Described herein are lateral III-N (e.g. GaN) devices having a III-N depleting layer, for which the III-N material is formed in an N-polar orientation. The III-N device includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N depleting layer. The III-N channel layer includes a 2DEG channel formed therein. The III-N device includes a source electrode and a drain electrode, each of which being electrically connected to the 2DEG channel, and a gate electrode between the source and the drain electrodes, the gate being over the III-N layer structure. The p-type III-N depleting layer includes a first portion that is between the gate and the drain electrode and the p-type III-N depleting layer is electrically connected to the gate electrode and electrically isolated from the source and drain electrodes.

What is claimed is: 
     
         1 . A III-N device, comprising:
 a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N depleting layer, wherein the III-N channel layer includes a 2DEG channel formed therein;   a source electrode and a drain electrode, each of which being electrically connected to the 2DEG channel;   a gate electrode between the source and the drain, the gate being over the III-N layer structure; wherein   the p-type III-N depleting layer includes a first portion that is between the gate electrode and the drain electrode; and   the p-type III-N depleting layer is electrically connected to the gate electrode and electrically isolated from the source and drain electrodes.   
     
     
         2 . The device of  claim 1 , wherein the III-N material structure is grown in an N-polar orientation. 
     
     
         3 . The device of  claim 1 , wherein a dopant concentration in the p-type III-N depleting layer is such that an areal p-type doping density in the p-type III-N layer is in the range of 10-150% of an areal sheet charge density of mobile charge in the 2DEG channel. 
     
     
         4 . The device of  claim 1 , further comprising a first Al x Ga 1-x N layer between the p-type III-N depleting layer and the III-N channel layer, wherein x is between 0.5 and 1, and the thickness of the Al x Ga 1-x N layer is between 0.5 nm and 5 nm. 
     
     
         5 . The device of  claim 4 , further comprising an n-type GaN layer between the gate electrode and the p-type III-N depleting layer. 
     
     
         6 . The device of  claim 5 , further comprising a second Al x Ga 1-x N layer between the n-type GaN layer and the p-type III-N depleting layer, wherein x is between 0.5 and 1, and the thickness of the Al x Ga 1-x N layer is between 0.5 nm and 5 nm. 
     
     
         7 . The device of  claim 6 , further comprises a second n-type GaN layer between the first n-type GaN layer and the second Al y Ga 1-y N layer, and a second p-type GaN layer between the p-type III-N depleting layer and the second Al y Ga 1-y N layer, wherein the second n-type GaN layer and the second p-type GaN layer have a doping density greater than the n-type GaN layer and the p-type III-N depleting layer. 
     
     
         8 . The device of  claim 1 , wherein the p-type III-N depleting layer includes a first end adjacent the drain electrode and a separation from the first end to the drain electrode is between 0.5 μm and 5 μm. 
     
     
         9 . The device of  claim 8 , wherein the gate electrode includes a field plate, and the field plate at least partially extends over the first portion of the p-type III-N depleting layer. 
     
     
         10 . The device of  claim 7 , wherein the drain electrode includes a field plate, and a portion of the field plate at least partially extends over the first portion of the p-type III-N depleting layer. 
     
     
         11 . The device of  claim 8 , wherein a sidewall angle of the first end relative to a bottom surface of the p-type III-N depleting layer is between 10-80 degrees. 
     
     
         12 . The device of  claim 1 , wherein the p-type III-N depleting layer includes a plurality of p-type layers over the III-N channel layer where each layer is separated by an Al x Ga 1-x N layer, wherein x is between 0.5 and 1, and the thickness of the Al x Ga 1-x N layer is between 0.5 nm and 5 nm. 
     
     
         13 . The device of  claim 12 , where each plurality of p-type layers includes a first end adjacent to the drain electrode, and the separation of the first end to the drain electrode increases from the p-type layer proximal the III-N channel layer to the p-type layer distal the III-N channel layer. 
     
     
         14 . A transistor, comprising:
 an N-polar III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer;   a source electrode and a drain electrode;   a gate electrode between the source and the drain, the gate being over the III-N layer structure and the p-type III-N layer is electrically connected to the gate electrode; and   a 2DEG channel in the III-N channel layer, wherein the N-polar III-N layer structure is configure such that the 2DEG channel extends continuously from the source electrode to the drain electrode when the gate is biased at 0V with respect to the source.   
     
     
         15 . The transistor of  claim 14 , wherein the p-type III-N layer includes at least a first portion between the gate electrode and the drain electrode. 
     
     
         16 . A transistor, comprising:
 a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N depleting layer, wherein the III-N channel layer includes a 2DEG channel formed therein;   a source electrode and a drain electrode, each of which being electrically connected to the 2DEG channel;   a gate electrode between the source and the drain, the gate being over the III-N layer structure; wherein   a first portion of the p-type III-N depleting layer is electrically connected to the gate electrode; and   a second portion of the p-type III-N depleting layer is electrically connected to the drain electrode; and   the first portion and the second portion are electrically isolated from each other.   
     
     
         17 . The transistor of  claim 16 , wherein a separation between the first portion of the III-N depleting layer and the second portion of the III-N depleting layer is between 0.5 μm and 5 μm. 
     
     
         18 . The transistor of  claim 17 , further comprising a first n-type GaN layer between the gate electrode and the first portion of the p-type III-N depleting layer, and a second n-type GaN layer between the drain electrode and the second portion of the III-N depleting layer. 
     
     
         19 . The transistor of  claim 18 , wherein the gate electrode is electrically connected to the first portion of the p-type III-N depleting layer with a tunnel junction and the drain electrode is electrically connected to the second portion of the III-N depleting layer with a tunnel junction. 
     
     
         20 . A III-N device comprising:
 a III-N layer structure comprising a III-N channel layer and a 2DEG channel therein, a III-N barrier layer under the III-N channel layer, and a p-type III-N layer over the III-N channel layer;   a source electrode and a drain electrode; and   a gate electrode between the source electrode and the drain electrode, the gate being over the III-N layer structure and electrically connected to the p-type III-N layer; wherein   the p-type III-N layer includes a first portion that is between the gate and the drain electrodes;   wherein the III-N device has a negative threshold voltage; and   wherein the III-N device is configured such that;   when the gate is biased relative to the source electrode at a negative voltage above a first minimum voltage, the 2DEG channel extends continuously from the source electrode to the drain electrode; and   when the gate is biased relative to the source electrode at a voltage below the first minimum voltage and above the threshold voltage, the p-type III-N layer is depleted of holes in the device region between the gate and drain electrodes.   
     
     
         21 . The device of  claim 20 , wherein the first minimum voltage is below −5V. 
     
     
         22 . The device of  claim 20 , wherein the device is configured such that, when the gate is biased above the first minimum voltage and the drain electrode is biased above a second minimum voltage, the p-type III-N layer is depleted of holes in the device region between the gate and drain electrode. 
     
     
         23 . The device of  claim 22 , wherein the second minimum voltage is above 5V.