Semiconductor device

Abstract

A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first enhancement-type element having a first control terminal and a pair of first main terminals, one of the first main terminals being connected to a region having a first potential, another of the first main terminals being connected to a first node, and the first control terminal being connected to a second node;   a second depletion-type element having a second control terminal and a pair of second main terminals, one of the second main terminals being connected to the first node, and another of the second main terminals being connected to the second node;   a first depletion-type element having a third control terminal and a pair of third main terminals, one of the third main terminals being connected to the second node, and the third control terminal being connected to a region having a second potential;   a first resistor portion having a plurality of resistor elements connected in series, and having one end connected to another of the third main terminals of the first depletion-type element, and another end connected to the region having the second potential, a region between the plurality of resistor elements being connected to the control terminal of the second depletion-type element; and   a first inverter having an input that is connected to the first node and outputting a reset signal.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a second enhancement-type element having a seventh control terminal and a pair of seventh main terminals, one of the seventh main terminals being connected to the first node, and the seventh control terminal being connected to another of the third main terminals of the first depletion-type element; and   a third enhancement-type element having an eighth control terminal and a pair of eighth main terminals, one of the eighth main terminals being connected to the region having the first potential, another of the eighth main terminals being connected to another of the seventh main terminals, and the eighth control terminal being connected to an output of the first inverter.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the seventh control terminal of the second enhancement-type element and the other of the third main terminals of the first depletion-type element are connected via a second resistor portion.